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soc.git
2021-03-18
Luke Kenneth...
remove nmigen-type-annotations temporarily
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2021-03-18
Luke Kenneth...
add option to move RS in CSV file reading, for compatib...
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2021-03-17
Luke Kenneth...
correct comments
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2021-03-17
Luke Kenneth...
re-enable SVP64 ISACaller predicate tests
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2021-03-17
Luke Kenneth...
add ascii graphic for extsw svp64 operation
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2021-03-17
Luke Kenneth...
add more explanatory comments
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2021-03-17
Luke Kenneth...
add twin-predicated extsw SVP64 ISACaller unit test
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2021-03-17
Luke Kenneth...
add SVP64 dststep incrementing in PowerDecoder2, Testis...
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2021-03-17
Luke Kenneth...
add CR-based predication to ISACaller
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2021-03-17
Tobias Platen
cleanup raduxmmu._walk_tree
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2021-03-17
Tobias Platen
create iterative mmu lookup loop
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2021-03-17
Luke Kenneth...
add SVP64 INT-style predication to ISACaller
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2021-03-17
Luke Kenneth...
add predication SVP64 unit test
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2021-03-17
Luke Kenneth...
add predication read ports (CR and INT)
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2021-03-17
Luke Kenneth...
whoops shift has to be done at same bitwidth
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2021-03-17
Luke Kenneth...
split out new_lookup function
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2021-03-17
Luke Kenneth...
link up SVP64 RM Mode decoding into PowerDecoder2
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2021-03-17
Luke Kenneth...
add priv and mode to RADIXMMU
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2021-03-17
Luke Kenneth...
add instr_fetch mode to ISACaller Mem and RADIXMMU
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2021-03-17
Luke Kenneth...
whitespace
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2021-03-17
Luke Kenneth...
add in SVP64 RM Mode decoder
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2021-03-16
Tobias Platen
radixmmu: detect badtree
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2021-03-16
Tobias Platen
add valid, leaf to loop
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2021-03-16
Cesar Strauss
Use symbolic values for subfields and bits
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2021-03-16
Cesar Strauss
Add subfield and bit definitions for the SVP64 RM mode...
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2021-03-16
Cesar Strauss
Define and initialise the mode variable, to be used...
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2021-03-16
Cesar Strauss
Rename class so it does not clash with the enum
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2021-03-15
Cesar Strauss
Fix import
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2021-03-15
Tobias Platen
add rpte bitfields valid and leaf
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2021-03-14
Luke Kenneth...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-14
Luke Kenneth...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-14
Cesar Strauss
Activate the VL==0 loop with any SVP64 prefix whatsoever
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2021-03-13
Luke Kenneth...
add setvl unit test assertions, add 2nd test
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2021-03-13
Luke Kenneth...
get first revision setvl operational in ISACaller
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2021-03-13
Luke Kenneth...
add setvl-to-long converter in SVP64Asm (sigh)
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2021-03-13
Luke Kenneth...
add setvl unit test
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2021-03-13
Luke Kenneth...
update submodule to include simplev setvl
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2021-03-13
Luke Kenneth...
include SVSTATE in namespace, passing to ISACaller
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2021-03-12
Jacob Lifshay
update submodule
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2021-03-12
Jacob Lifshay
add setvl to decoder
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2021-03-12
Jacob Lifshay
autoformat code
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2021-03-12
Luke Kenneth...
add OP_SETVL to MicrOp in power_enums.py
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2021-03-12
Luke Kenneth...
add ability to set and distinguish RT=0 (RT_OR_ZERO...
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2021-03-12
Luke Kenneth...
use PowerDecoder2.loop_continue instead of no_out_vec
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2021-03-12
Luke Kenneth...
remove old code
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2021-03-12
Luke Kenneth...
remove old code
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2021-03-12
Luke Kenneth...
remove old code
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2021-03-12
Luke Kenneth...
add more sophisticated checking of whether SVP64 loop...
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2021-03-12
Luke Kenneth...
**FOR NOW** LD/ST relies on detection of twin-predicati...
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2021-03-12
Luke Kenneth...
decoding of svp64 reg by name has to occur after immedi...
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2021-03-12
Jacob Lifshay
add forgotten PO (primary opcode) field to DecodeFields
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2021-03-11
Cesar Strauss
Bring a few test cases from test_caller_64.py
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2021-03-11
Cesar Strauss
Test case for two successive SV instructions
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2021-03-11
Luke Kenneth...
add link of RA_OR_ZERO SVP64 detection
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2021-03-11
Luke Kenneth...
add detection of whether *full* 7-bit of RA is zero...
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2021-03-11
Luke Kenneth...
add in SVP64 LD/ST basic test for ISACaller
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2021-03-11
Luke Kenneth...
whoops sort out when svstate not active in ISACaller
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2021-03-11
Luke Kenneth...
whoops PIDR is defined as 32-bits in SPRs.csv (and...
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2021-03-11
Luke Kenneth...
add understanding of LDST immediates to SVP64ASM
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2021-03-11
Tobias Platen
fix runtime error
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2021-03-10
Tobias Platen
radix: reading first page table entry
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2021-03-10
Luke Kenneth...
add walk_tree arguments it needs
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2021-03-09
Luke Kenneth...
fix address must convert to SelectableInt
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2021-03-09
Luke Kenneth...
call decode_ptre on address to obtain shift, mbits...
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2021-03-09
Tobias Platen
whitespace
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2021-03-09
Tobias Platen
RADIX: call self._walk_tree in ld and st
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2021-03-09
Luke Kenneth...
debug radix mmu ISACaller
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2021-03-09
Tobias Platen
comment out broken spr code
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2021-03-09
Tobias Platen
_walk_tree: access sprs
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2021-03-09
Luke Kenneth...
create first check_perms RADIX ISACaller function
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2021-03-09
Luke Kenneth...
move Mem class out of ISACaller
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2021-03-09
Luke Kenneth...
cleanup imports
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2021-03-09
Luke Kenneth...
move ISACaller RADIX MMU class to separate module
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2021-03-09
Luke Kenneth...
add pgtable and pte calculation to RADIX ISACaller
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2021-03-09
Cesar Strauss
Enable VL==0 vector instruction skip test case
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2021-03-09
Cesar Strauss
Add some extra debug traces to the GTKWave document
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2021-03-09
Cesar Strauss
Create a new signal for the Simulator to wait on
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2021-03-08
Luke Kenneth...
start adding _get_prtable_addr
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2021-03-08
Luke Kenneth...
actually make it possible to disable svp64 on commandli...
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2021-03-08
Luke Kenneth...
add option in TestRunner to disable svp64 via commandli...
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2021-03-08
Luke Kenneth...
add option to cut out SVP64 from PowerDecoder2
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2021-03-08
Luke Kenneth...
correct comments in sv.add rc=1
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2021-03-08
Cesar Strauss
Remove the unused internal insn_done signal
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2021-03-08
Cesar Strauss
Fix argument order to match function declaration
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2021-03-07
Cesar Strauss
Fix missing NIA update on ISACaller
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2021-03-07
Luke Kenneth...
whoops should be "make gitupdate"
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2021-03-07
Tobias Platen
RADIX: read SPRs
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2021-03-07
Tobias Platen
RADIX: implement memassign and call
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2021-03-07
Luke Kenneth...
add SVSTATE read to DMI interface
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2021-03-07
Cesar Strauss
Merge WAIT_RESET into INSN_FETCH on the Issue FSM
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2021-03-07
Luke Kenneth...
move DMI stuff to separate function in issuer.py
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2021-03-07
Luke Kenneth...
update comments in issuer.py
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2021-03-07
Luke Kenneth...
add Rc=1 SVP64 unit test to svp64_cases.py
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2021-03-07
Cesar Strauss
Implement the VL==0 loop
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2021-03-06
Cesar Strauss
Allow updating the PC and SVSTATE registers while stopped
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2021-03-06
Cesar Strauss
Enable the Simple-V loop test case
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2021-03-06
Cesar Strauss
Begin to implement the Simple-V loop
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2021-03-06
Cesar Strauss
Do not reset pc_changed and sv_changed at instruction end
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2021-03-06
Cesar Strauss
Make the raw opcode input port of the decoder stay...
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2021-03-06
Luke Kenneth...
remove blackbox attribute on SPBlock_512W64B8W
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