soc.git
2021-03-18 Luke Kenneth... remove nmigen-type-annotations temporarily
2021-03-18 Luke Kenneth... add option to move RS in CSV file reading, for compatib...
2021-03-17 Luke Kenneth... correct comments
2021-03-17 Luke Kenneth... re-enable SVP64 ISACaller predicate tests
2021-03-17 Luke Kenneth... add ascii graphic for extsw svp64 operation
2021-03-17 Luke Kenneth... add more explanatory comments
2021-03-17 Luke Kenneth... add twin-predicated extsw SVP64 ISACaller unit test
2021-03-17 Luke Kenneth... add SVP64 dststep incrementing in PowerDecoder2, Testis...
2021-03-17 Luke Kenneth... add CR-based predication to ISACaller
2021-03-17 Tobias Platencleanup raduxmmu._walk_tree
2021-03-17 Tobias Platencreate iterative mmu lookup loop
2021-03-17 Luke Kenneth... add SVP64 INT-style predication to ISACaller
2021-03-17 Luke Kenneth... add predication SVP64 unit test
2021-03-17 Luke Kenneth... add predication read ports (CR and INT)
2021-03-17 Luke Kenneth... whoops shift has to be done at same bitwidth
2021-03-17 Luke Kenneth... split out new_lookup function
2021-03-17 Luke Kenneth... link up SVP64 RM Mode decoding into PowerDecoder2
2021-03-17 Luke Kenneth... add priv and mode to RADIXMMU
2021-03-17 Luke Kenneth... add instr_fetch mode to ISACaller Mem and RADIXMMU
2021-03-17 Luke Kenneth... whitespace
2021-03-17 Luke Kenneth... add in SVP64 RM Mode decoder
2021-03-16 Tobias Platenradixmmu: detect badtree
2021-03-16 Tobias Platenadd valid, leaf to loop
2021-03-16 Cesar StraussUse symbolic values for subfields and bits
2021-03-16 Cesar StraussAdd subfield and bit definitions for the SVP64 RM mode...
2021-03-16 Cesar StraussDefine and initialise the mode variable, to be used...
2021-03-16 Cesar StraussRename class so it does not clash with the enum
2021-03-15 Cesar StraussFix import
2021-03-15 Tobias Platenadd rpte bitfields valid and leaf
2021-03-14 Luke Kenneth... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-14 Luke Kenneth... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-14 Cesar StraussActivate the VL==0 loop with any SVP64 prefix whatsoever
2021-03-13 Luke Kenneth... add setvl unit test assertions, add 2nd test
2021-03-13 Luke Kenneth... get first revision setvl operational in ISACaller
2021-03-13 Luke Kenneth... add setvl-to-long converter in SVP64Asm (sigh)
2021-03-13 Luke Kenneth... add setvl unit test
2021-03-13 Luke Kenneth... update submodule to include simplev setvl
2021-03-13 Luke Kenneth... include SVSTATE in namespace, passing to ISACaller
2021-03-12 Jacob Lifshayupdate submodule
2021-03-12 Jacob Lifshayadd setvl to decoder
2021-03-12 Jacob Lifshayautoformat code
2021-03-12 Luke Kenneth... add OP_SETVL to MicrOp in power_enums.py
2021-03-12 Luke Kenneth... add ability to set and distinguish RT=0 (RT_OR_ZERO...
2021-03-12 Luke Kenneth... use PowerDecoder2.loop_continue instead of no_out_vec
2021-03-12 Luke Kenneth... remove old code
2021-03-12 Luke Kenneth... remove old code
2021-03-12 Luke Kenneth... remove old code
2021-03-12 Luke Kenneth... add more sophisticated checking of whether SVP64 loop...
2021-03-12 Luke Kenneth... **FOR NOW** LD/ST relies on detection of twin-predicati...
2021-03-12 Luke Kenneth... decoding of svp64 reg by name has to occur after immedi...
2021-03-12 Jacob Lifshayadd forgotten PO (primary opcode) field to DecodeFields
2021-03-11 Cesar StraussBring a few test cases from test_caller_64.py
2021-03-11 Cesar StraussTest case for two successive SV instructions
2021-03-11 Luke Kenneth... add link of RA_OR_ZERO SVP64 detection
2021-03-11 Luke Kenneth... add detection of whether *full* 7-bit of RA is zero...
2021-03-11 Luke Kenneth... add in SVP64 LD/ST basic test for ISACaller
2021-03-11 Luke Kenneth... whoops sort out when svstate not active in ISACaller
2021-03-11 Luke Kenneth... whoops PIDR is defined as 32-bits in SPRs.csv (and...
2021-03-11 Luke Kenneth... add understanding of LDST immediates to SVP64ASM
2021-03-11 Tobias Platenfix runtime error
2021-03-10 Tobias Platenradix: reading first page table entry
2021-03-10 Luke Kenneth... add walk_tree arguments it needs
2021-03-09 Luke Kenneth... fix address must convert to SelectableInt
2021-03-09 Luke Kenneth... call decode_ptre on address to obtain shift, mbits...
2021-03-09 Tobias Platenwhitespace
2021-03-09 Tobias PlatenRADIX: call self._walk_tree in ld and st
2021-03-09 Luke Kenneth... debug radix mmu ISACaller
2021-03-09 Tobias Platencomment out broken spr code
2021-03-09 Tobias Platen_walk_tree: access sprs
2021-03-09 Luke Kenneth... create first check_perms RADIX ISACaller function
2021-03-09 Luke Kenneth... move Mem class out of ISACaller
2021-03-09 Luke Kenneth... cleanup imports
2021-03-09 Luke Kenneth... move ISACaller RADIX MMU class to separate module
2021-03-09 Luke Kenneth... add pgtable and pte calculation to RADIX ISACaller
2021-03-09 Cesar StraussEnable VL==0 vector instruction skip test case
2021-03-09 Cesar StraussAdd some extra debug traces to the GTKWave document
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on
2021-03-08 Luke Kenneth... start adding _get_prtable_addr
2021-03-08 Luke Kenneth... actually make it possible to disable svp64 on commandli...
2021-03-08 Luke Kenneth... add option in TestRunner to disable svp64 via commandli...
2021-03-08 Luke Kenneth... add option to cut out SVP64 from PowerDecoder2
2021-03-08 Luke Kenneth... correct comments in sv.add rc=1
2021-03-08 Cesar StraussRemove the unused internal insn_done signal
2021-03-08 Cesar StraussFix argument order to match function declaration
2021-03-07 Cesar StraussFix missing NIA update on ISACaller
2021-03-07 Luke Kenneth... whoops should be "make gitupdate"
2021-03-07 Tobias PlatenRADIX: read SPRs
2021-03-07 Tobias PlatenRADIX: implement memassign and call
2021-03-07 Luke Kenneth... add SVSTATE read to DMI interface
2021-03-07 Cesar StraussMerge WAIT_RESET into INSN_FETCH on the Issue FSM
2021-03-07 Luke Kenneth... move DMI stuff to separate function in issuer.py
2021-03-07 Luke Kenneth... update comments in issuer.py
2021-03-07 Luke Kenneth... add Rc=1 SVP64 unit test to svp64_cases.py
2021-03-07 Cesar StraussImplement the VL==0 loop
2021-03-06 Cesar StraussAllow updating the PC and SVSTATE registers while stopped
2021-03-06 Cesar StraussEnable the Simple-V loop test case
2021-03-06 Cesar StraussBegin to implement the Simple-V loop
2021-03-06 Cesar StraussDo not reset pc_changed and sv_changed at instruction end
2021-03-06 Cesar StraussMake the raw opcode input port of the decoder stay...
2021-03-06 Luke Kenneth... remove blackbox attribute on SPBlock_512W64B8W
next