| 2020-08-16 | 
Luke Kenneth...  | continue tidyup, comment removal/review.  use byte_reve...  | 
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| 2020-08-16 | 
Luke Kenneth...  | fix batch of syntax errors found by running mmu.py | 
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| 2020-08-16 | 
Luke Kenneth...  | begin tidyup, removing comments after line-by-line...  | 
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| 2020-08-15 | 
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | 
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| 2020-08-15 | 
Cole Poirier | mmu.py fix Cat() semantics fixes https://bugs.libre...  | 
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| 2020-08-15 | 
Luke Kenneth...  | thanks to daveshah, added simulation of dram | 
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| 2020-08-15 | 
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...  | 
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| 2020-08-15 | 
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...  | 
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| 2020-08-15 | 
Cole Poirier | mmu.py fixes https://bugs.libre-soc.org/show_bug.cgi...  | 
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| 2020-08-15 | 
Luke Kenneth...  | rather big change to interaction between regfile and...  | 
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| 2020-08-15 | 
Luke Kenneth...  | clear compalu data latch always on issue | 
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| 2020-08-15 | 
Cesar Strauss | Demonstrates string traces | 
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| 2020-08-15 | 
Cesar Strauss | Demonstrates adding extra debug signals traces to the...  | 
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| 2020-08-15 | 
Cesar Strauss | Demonstrates creating stylish GTKWave "save" files...  | 
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| 2020-08-14 | 
Luke Kenneth...  | remove latchregister, use sync to capture compunit...  | 
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| 2020-08-14 | 
Luke Kenneth...  | ha! "state" (pc, msr) not properly passed to core | 
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| 2020-08-14 | 
Luke Kenneth...  | drop in insn_state synchronously in issuer, at same...  | 
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| 2020-08-14 | 
Luke Kenneth...  | submodule update | 
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| 2020-08-14 | 
Luke Kenneth...  | hrfid unit test sets up HSRR0 and HSRR1 | 
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| 2020-08-14 | 
Luke Kenneth...  | bad hack to get HSRR0/1 to be "same" as SRR0/1 | 
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| 2020-08-14 | 
Luke Kenneth...  | bug in isa parser not recognising MSR as declared variable | 
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| 2020-08-14 | 
Luke Kenneth...  | hack to get hrfid not to alter msr 51 | 
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| 2020-08-14 | 
Luke Kenneth...  | stop trying to read swap files | 
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| 2020-08-14 | 
Luke Kenneth...  | sync on alu results in compalu | 
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| 2020-08-14 | 
Luke Kenneth...  | update submodule, add hrfid | 
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| 2020-08-14 | 
Luke Kenneth...  | update submodule, add hrfid | 
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| 2020-08-14 | 
Luke Kenneth...  | finally, fix decoder combinatorial loop | 
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| 2020-08-14 | 
Luke Kenneth...  | fix test_compunit.py after moving decoder rdflags function | 
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| 2020-08-14 | 
Luke Kenneth...  | add hrfid unit test | 
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| 2020-08-14 | 
Luke Kenneth...  | sync up the core decode-execute state, | 
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| 2020-08-14 | 
Luke Kenneth...  | move instruction decoder out of core | 
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| 2020-08-14 | 
Luke Kenneth...  | move regspec / rdflag decoding functions out of PowerDe...  | 
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| 2020-08-14 | 
Luke Kenneth...  | sort out instruction stop/cancel when adding a new...  | 
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| 2020-08-14 | 
Luke Kenneth...  | put multi-ports back (for read) on int and fast regfiles | 
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| 2020-08-14 | 
Luke Kenneth...  | reduce decoder pathways when exception occurs | 
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| 2020-08-14 | 
Luke Kenneth...  | divide shiftrot pipeline into 2 (simple last) | 
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| 2020-08-14 | 
Luke Kenneth...  | divide alu pipeline into 2 (simple last) | 
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| 2020-08-14 | 
Luke Kenneth...  | divide logical pipe into 2 (simple phase last) | 
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| 2020-08-14 | 
Jacob Lifshay | running the simulator works! | 
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| 2020-08-13 | 
Jacob Lifshay | add --cpu=libresoc to Makefile | 
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| 2020-08-13 | 
Luke Kenneth...  | fix dmi reg read | 
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| 2020-08-13 | 
Luke Kenneth...  | code-shuffle | 
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| 2020-08-13 | 
Luke Kenneth...  | remove use of latchregigister, replace with sync on...  | 
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| 2020-08-13 | 
Luke Kenneth...  | sync on pc writing when changed | 
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| 2020-08-13 | 
Cole Poirier | dcache.py add initial imports | 
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| 2020-08-13 | 
Cole Poirier | mem_types.py add more types from common.vhdl | 
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| 2020-08-13 | 
Cole Poirier | move memory related types from mmu.py into new file...  | 
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| 2020-08-13 | 
Luke Kenneth...  | sync on reset in compalu | 
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| 2020-08-13 | 
Luke Kenneth...  | add forwarding-bus mode to Regfile Memory (and disable it) | 
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| 2020-08-13 | 
Luke Kenneth...  | sync on port interface address in ld/st compunit, and...  | 
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| 2020-08-13 | 
Luke Kenneth...  | another sync to cut latency | 
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| 2020-08-13 | 
Cole Poirier | Initial commit of translation of microwatt dcache.vhdl...  | 
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| 2020-08-13 | 
Luke Kenneth...  | remove latchregister, sync src oper_i into MultiCompUnit | 
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| 2020-08-13 | 
Luke Kenneth...  | minor tidyup on alu compunit: | 
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| 2020-08-13 | 
Luke Kenneth...  | plenty of time to wait for operand, so use "sync" in...  | 
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| 2020-08-13 | 
Luke Kenneth...  | sigh.  convert Fast regfile to binary | 
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| 2020-08-13 | 
Luke Kenneth...  | sync on read of regfile ports | 
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| 2020-08-13 | 
Luke Kenneth...  | sigh.  convert INT regfile to binary addressing | 
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| 2020-08-13 | 
Luke Kenneth...  | create a RegFileMem class that uses Memory | 
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| 2020-08-12 | 
Jacob Lifshay | add run_sim to Makefile | 
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| 2020-08-12 | 
Cole Poirier | mmu.py add skeleton sim and test functions from regfile...  | 
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| 2020-08-12 | 
Cole Poirier | Delete unnecessary mmu dir, move mmu.py out of mmu...  | 
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| 2020-08-12 | 
Cole Poirier | Revert "Remove mmu dir and associated mmu/test/ dir...  | 
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| 2020-08-12 | 
Cole Poirier | Remove mmu dir and associated mmu/test/ dir | 
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| 2020-08-12 | 
Cole Poirier | Remove rst signals, fix len of hex Consts, fix variable...  | 
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| 2020-08-12 | 
Cole Poirier | Create dir experiment/mmu then mmu/test with skeleton...  | 
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| 2020-08-12 | 
Cole Poirier | mmu.py add RecordObject classes from common.vhdl input...  | 
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| 2020-08-12 | 
Cole Poirier | mmu.py remove TODOs for vhdl (others => '0') as they...  | 
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| 2020-08-12 | 
Cole Poirier | mmu.py fix or(block of logic) to be (block of logic...  | 
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| 2020-08-12 | 
Cole Poirier | mmu.py fix length of hex const https://bugs.libre-soc...  | 
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| 2020-08-12 | 
Cole Poirier | mmu.py remove class AddrShifter | 
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| 2020-08-12 | 
Cole Poirier | Fix typo in mmu.py | 
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| 2020-08-11 | 
Cole Poirier | mmu.py fix formatting, use Cat() where '&' in mmu.vhdl | 
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| 2020-08-11 | 
Tobias Platen | initial version of L0CacheBuffer2 | 
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| 2020-08-11 | 
Luke Kenneth...  | sigh, remove yet another int regfile read port | 
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| 2020-08-11 | 
Luke Kenneth...  | massive reduction in gate count by using alternative...  | 
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| 2020-08-11 | 
Luke Kenneth...  | reduce regfile port usage for INT and FAST | 
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| 2020-08-11 | 
Luke Kenneth...  | prepare write ports to be shared | 
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| 2020-08-11 | 
Luke Kenneth...  | move write regfile picker creation to new function | 
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| 2020-08-11 | 
Luke Kenneth...  | reduce regfile ports by creating separate STATE regfile | 
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| 2020-08-11 | 
Luke Kenneth...  | whoops fix change of variable (state) msr/pc | 
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| 2020-08-11 | 
Luke Kenneth...  | reducing regfile port usage by sharing read ports | 
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| 2020-08-10 | 
Samuel A. Falvo II | WIP!!  Make MUL pipeline proof run again. | 
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| 2020-08-10 | 
Cole Poirier | Fix typo in mmu.py | 
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| 2020-08-10 | 
Cole Poirier | Fix typo mmu.py | 
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| 2020-08-10 | 
Cole Poirier | Global search and replace (^, |), fixes bug 450 comment...  | 
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| 2020-08-10 | 
Cole Poirier | fix bug 450 comments 8,9,10 | 
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| 2020-08-10 | 
Cole Poirier | Fix bug 450 comment 7 | 
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| 2020-08-10 | 
Cole Poirier | mmu.py add line I forgot to translate from mmu.vhdl | 
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| 2020-08-10 | 
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | 
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| 2020-08-10 | 
Cole Poirier | mmu.vhdl translation to mmu.py 95 percent complete | 
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| 2020-08-09 | 
Luke Kenneth...  | stop combinatorial loop in pi2ls | 
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| 2020-08-09 | 
Luke Kenneth...  | write pulse in issuer | 
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| 2020-08-09 | 
Luke Kenneth...  | fix combinatorial loop in ldst compunit | 
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| 2020-08-09 | 
Luke Kenneth...  | use rising edge detection on st go_i/rel_o | 
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| 2020-08-09 | 
Luke Kenneth...  | add logical test issuer case | 
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| 2020-08-09 | 
Luke Kenneth...  | get rid of MSR read combinatorial loop | 
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| 2020-08-09 | 
Luke Kenneth...  | delay go_st by one cycle, break combinatorial loop | 
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| 2020-08-09 | 
Luke Kenneth...  | divwo case makes test_issuer stay busy! | 
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| 2020-08-09 | 
Luke Kenneth...  | add extra divwo regression test | 
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| next |