| 2021-06-09 |
Jean-Paul Chaput | Add a case in the build script to fit my environment... |
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| 2021-06-09 |
Jean-Paul Chaput | Remove files that are now copied from other locations. |
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| 2021-06-08 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-06-08 |
Jean-Paul Chaput | Adpapt e9/TSMC doDesign to the new size of the SRAMs... |
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| 2021-06-06 |
Luke Kenneth... | argh, nsxlib cannot cope with 3 clocks! |
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| 2021-06-05 |
Luke Kenneth... | add vss/vdd as pins, gets the net into the VST |
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| 2021-06-05 |
Luke Kenneth... | set power type in fake pll vdd/vss |
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| 2021-06-05 |
Luke Kenneth... | whoops, fake pll/mem need vss/vdd |
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| 2021-06-05 |
Luke Kenneth... | whoops naming pads different from nets is important |
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| 2021-06-05 |
Luke Kenneth... | sigh trying to find the right clock line |
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| 2021-06-05 |
Luke Kenneth... | more comments |
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| 2021-06-05 |
Luke Kenneth... | comment about por_clk |
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| 2021-06-05 |
Luke Kenneth... | correct clock name for H-Tree in ls180 |
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| 2021-06-05 |
Luke Kenneth... | sort out clock names in experiments10_verilog |
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| 2021-06-05 |
Luke Kenneth... | add coresync_clk to list of HTree |
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| 2021-06-05 |
Luke Kenneth... | add dummy pll to experiments10_verilog |
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| 2021-06-05 |
Luke Kenneth... | set various clocks to use H-Tree |
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| 2021-06-05 |
Luke Kenneth... | add dummy (fake) PLL to experiments10_verilog for testing |
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| 2021-06-04 |
Jean-Paul Chaput | Updated experiments12 for the latest Coriolis. |
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| 2021-06-04 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-06-04 |
Jean-Paul Chaput | Updated configuration suited for experiment9/tsmc_c018. |
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| 2021-06-03 |
Luke Kenneth... | add 4ksram recon script in tsmc_c018 as well |
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| 2021-06-03 |
Luke Kenneth... | add build_full_4ksram_recon.sh to copy over Staf re... |
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| 2021-06-03 |
Luke Kenneth... | rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk |
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| 2021-06-03 |
Staf Verhaegen | Reroute clk so PLL output clock is used as sys_clk. |
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| 2021-06-03 |
Staf Verhaegen | Duplicate file before patching for clock rerouting. |
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| 2021-06-03 |
Luke Kenneth... | rename ref in fake-pll to ref_v |
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| 2021-06-03 |
Luke Kenneth... | update libresoc.v to use sys_clk for main core |
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| 2021-06-03 |
Luke Kenneth... | change ref to ref_v in PLL (keyword) |
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| 2021-05-27 |
Luke Kenneth... | set other nets to input in fake 4k SRAM cell |
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| 2021-05-27 |
Luke Kenneth... | add TODO into tsmc_c018 coriolis2 settings.py |
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| 2021-05-27 |
Luke Kenneth... | update libresoc.v |
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| 2021-05-27 |
Luke Kenneth... | set fake-mem LibreSOCMem output q as a Net Output |
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| 2021-05-27 |
Luke Kenneth... | set fake PLL Master Cell directions explicitly |
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| 2021-05-26 |
Luke Kenneth... | clk_sel_i in TestIssuer was one bit not 2 |
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| 2021-05-26 |
Luke Kenneth... | remove sram4k wb err (unused anyway) |
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| 2021-05-26 |
Luke Kenneth... | appears to be missing libresoc from NETLISTS in Makefile |
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| 2021-05-25 |
Luke Kenneth... | attempt better grid alignment for fake cells |
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| 2021-05-25 |
Luke Kenneth... | change cell sizes to grid layout (?) |
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| 2021-05-25 |
Luke Kenneth... | increase not-connected pads by one |
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| 2021-05-25 |
Luke Kenneth... | add fake pll symlink |
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| 2021-05-25 |
Luke Kenneth... | rename pll out signal to out_v in "fake" pll cell |
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| 2021-05-25 |
Luke Kenneth... | rename PLL out to out_v in test_issuer |
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| 2021-05-25 |
Luke Kenneth... | rename pll blackbox out to out_v |
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| 2021-05-24 |
Luke Kenneth... | disappearing signal from pll, attempt to get it back |
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| 2021-05-24 |
Luke Kenneth... | remove "*" net from fake-pll cell, it ends up in the... |
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| 2021-05-24 |
Luke Kenneth... | round to 0.135 cell grid? |
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| 2021-05-24 |
Luke Kenneth... | rename cell to "real_pll" to avoid conflict with cell... |
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| 2021-05-24 |
Luke Kenneth... | add dummy/fake/ghost PLL blackbox cell |
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| 2021-05-22 |
Luke Kenneth... | rename PLL pad names |
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| 2021-05-22 |
Luke Kenneth... | correct PLL names |
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| 2021-05-22 |
Luke Kenneth... | re-add 4k sram |
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| 2021-05-22 |
Luke Kenneth... | annoying rename of pll analog pin |
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| 2021-05-22 |
Luke Kenneth... | manually rename ls180sram4k module to ls180 |
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| 2021-05-22 |
Luke Kenneth... | submodule update |
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| 2021-05-22 |
Luke Kenneth... | update PLL to use submodule Instance |
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| 2021-04-30 |
Luke Kenneth... | do an SRAM search by looking for matching along the... |
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| 2021-04-30 |
Luke Kenneth... | 4k sram build |
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| 2021-04-30 |
Luke Kenneth... | use "make view" not "make vst" |
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| 2021-04-30 |
Luke Kenneth... | add fake LibreSOCMem library to freepdk_c4m45 |
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| 2021-04-30 |
Luke Kenneth... | add symlink to "fake" LibreSOCMem |
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| 2021-04-30 |
Luke Kenneth... | enabling experiments9 new LibreSOCMem fake blackbox... |
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| 2021-04-30 |
Luke Kenneth... | using renamed (single) spblock_512w64b8w |
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| 2021-04-30 |
Luke Kenneth... | using new single spblock_512xxx in experiments9 |
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| 2021-04-30 |
Luke Kenneth... | add complete series of pins onto fake SRAM |
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| 2021-04-28 |
Luke Kenneth... | first experiment creating a LibreSOCMem library with... |
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| 2021-04-28 |
Luke Kenneth... | create function which pre-creates the blackbox cells |
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| 2021-04-28 |
Luke Kenneth... | name everything back to spblock_512w64b8w now that... |
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| 2021-04-28 |
Luke Kenneth... | rename spblock modules to just straight spblock_512w64b... |
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| 2021-04-28 |
Luke Kenneth... | also add createSRAMblocks to freepdk_c4m45 |
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| 2021-04-28 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-04-28 |
Jean-Paul Chaput | Management of SRAMs block at Coriolis devel. |
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| 2021-04-28 |
Luke Kenneth... | add vbe spblock models to non_generated and build scripts |
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| 2021-04-28 |
Luke Kenneth... | shrinking regfile sizes some more |
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| 2021-04-27 |
Luke Kenneth... | add blackbox attribute to spblock512*.v |
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| 2021-04-27 |
Luke Kenneth... | also add blackboxes spblock512* etc. |
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| 2021-04-27 |
Luke Kenneth... | add copying over of spblock*.v and pll.v to build scripts |
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| 2021-04-25 |
Luke Kenneth... | submodule update |
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| 2021-04-25 |
Jean-Paul Chaput | Correct setup for experiment9/freepdk_c4m45, restrict... |
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| 2021-04-24 |
Luke Kenneth... | update submodule |
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| 2021-04-24 |
Luke Kenneth... | cleanup mksyms.sh to include FreePDK_C4M45 |
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| 2021-04-24 |
Luke Kenneth... | add export of PDKMASTER_TOP to experiments9/freepdk_c4m45 |
commit | commitdiff | tree |
| 2021-04-24 |
Luke Kenneth... | correct relative link to FreePDK45_c4m45, use submodule |
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| 2021-04-24 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-04-24 |
Jean-Paul Chaput | Forgot to update experiments9 doDesign file for FreePDK 45. |
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| 2021-04-24 |
Jean-Paul Chaput | Keep in synch with the latest Coriolis. SRAM models... |
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| 2021-04-24 |
Jean-Paul Chaput | Correct settings for experiment10_verilog & FreePDK45. |
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| 2021-04-22 |
Luke Kenneth... | make placement of SRAMs optional, and PLL as well,... |
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| 2021-04-20 |
Luke Kenneth... | manually comment out pll and sdcard pins |
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| 2021-04-19 |
Staf Verhaegen | experiments10_verilog/freepdk_c4m45: Add link for add.py. |
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| 2021-04-19 |
Staf Verhaegen | Top layer -> metal6 |
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| 2021-04-19 |
Staf Verhaegen | experiments9/freepdk_c4m45: Reduce core size. |
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| 2021-04-19 |
Luke Kenneth... | add SPBlock512 instance generator |
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| 2021-04-19 |
Luke Kenneth... | code-comments |
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| 2021-04-19 |
Luke Kenneth... | add two SRAMs, document how to do more |
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| 2021-04-18 |
Luke Kenneth... | argh, found the blackbox problem: yosys is "doing the... |
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| 2021-04-18 |
Luke Kenneth... | try renaming spblock without the underscore |
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| 2021-04-18 |
Luke Kenneth... | try changing layout of blackbox spblock_512w64b8w |
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| 2021-04-18 |
Luke Kenneth... | experimenting with blackboxes |
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| 2021-04-18 |
Luke Kenneth... | rename spblock_512w64b8w, and vco_test_ana for pll |
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