2020-06-09 |
Luke Kenneth... | expand LenExpand (haha) to cover bytes, with an argumen... |
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2020-06-09 |
Tobias Platen | elaborate function for DualPortSplitter |
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2020-06-09 |
Cesar Strauss | Avoid a combinatorial loop on valid_o |
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2020-06-09 |
Tobias Platen | fixes for DualPortSplitter |
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2020-06-09 |
Luke Kenneth... | make DataMerger record reset_less |
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2020-06-09 |
Luke Kenneth... | add truncaddr function to L0CacheBuffer test class |
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2020-06-09 |
Luke Kenneth... | add convenience variables in TestMemory |
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2020-06-09 |
Luke Kenneth... | map LDST len directly, rather than go through a switch... |
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2020-06-09 |
Luke Kenneth... | correct local variable references |
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2020-06-09 |
Luke Kenneth... | bit more on TRAP handling (preparing priv instruction) |
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2020-06-08 |
Luke Kenneth... | add traptype and trapaddr to PowerDecoder2. idea is... |
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2020-06-08 |
Luke Kenneth... | add traptype and trapaddr to trap_input_data.py |
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2020-06-08 |
Luke Kenneth... | add "instr_is_privileged" to power_decoder2 (untested) |
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2020-06-08 |
Luke Kenneth... | use 2nd shortened convenience variable in PowerDecoder2 |
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2020-06-08 |
Luke Kenneth... | use shortened convenience variable in PowerDecoder2 |
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2020-06-08 |
Luke Kenneth... | re-add unit tests back in |
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2020-06-08 |
Luke Kenneth... | add comment docstring about POWER9 simulator |
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2020-06-08 |
Luke Kenneth... | more verbose debug information tracking down SO/OV... |
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2020-06-08 |
Luke Kenneth... | whoops, overflow-decode (handle_overflow) needed to... |
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2020-06-08 |
Michael Nolan | Add register assertions, fix broken tests |
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2020-06-08 |
Michael Nolan | Update to latest wiki version |
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2020-06-08 |
Michael Nolan | Restore test_sim.py, begin modifying it for testing... |
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2020-06-08 |
Luke Kenneth... | add CA/CA32 to write regs fields in parser |
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2020-06-08 |
Luke Kenneth... | check that carry has already been done or not by the... |
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2020-06-08 |
Luke Kenneth... | code-morph test_core for XER bit clarity |
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2020-06-08 |
Luke Kenneth... | set only the SO bit as sticky, not the OV flags as... |
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2020-06-08 |
Luke Kenneth... | copy 64-bit OV, try creating 32-bit OV32 in |
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2020-06-08 |
Luke Kenneth... | clarify using microwatt calc_ov function. |
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2020-06-08 |
Luke Kenneth... | added check which shows that OV32 in "adde." is not... |
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2020-06-08 |
Luke Kenneth... | found section in 3.0B PDF that refers to "Program Inter... |
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2020-06-08 |
Luke Kenneth... | move datamerger proof into standard directory location... |
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2020-06-08 |
Luke Kenneth... | copy MSR into SRR1 in trap function |
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2020-06-08 |
colepoirier | Fix spelling |
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2020-06-07 |
Luke Kenneth... | update trap with comments |
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2020-06-07 |
Luke Kenneth... | update comments |
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2020-06-07 |
colepoirier | Add TrapMainStage.trap() convenience function to set... |
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2020-06-07 |
Cesar Strauss | Assign the one-clock delay operation from ADD to SHR |
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2020-06-07 |
Luke Kenneth... | assert XER SO/OV/CA registers, check these are ok ... |
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2020-06-07 |
Luke Kenneth... | add debug print statements, re-enable all tests in... |
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2020-06-07 |
Luke Kenneth... | resolved CR mfcr lookup bug (was in power_decoder. ??) |
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2020-06-07 |
Cesar Strauss | Try responding with ready_i on the same cycle as valid_o |
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2020-06-07 |
Cesar Strauss | Assert valid_o one clock early, as alu_done is asserted |
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2020-06-07 |
Cesar Strauss | Make the test ALU conform to the valid/ready protocol |
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2020-06-07 |
colepoirier | Add back test cases to cookie-cut from for fu/trap... |
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2020-06-07 |
Luke Kenneth... | add extra tests for mcrf: shows bug is not directly... |
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2020-06-07 |
Luke Kenneth... | how odd. just adding CA32 to self.namespace seems... |
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2020-06-07 |
Luke Kenneth... | add extra args to ISA in branch test_pipe_caller |
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2020-06-07 |
Luke Kenneth... | add msr to ISA in test_core.py |
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2020-06-07 |
Luke Kenneth... | wark-wark, do not & rs[0] into carry-out from rotator |
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2020-06-07 |
Luke Kenneth... | ha! set XER CA/CA32 in simulator from output.value... |
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2020-06-07 |
Luke Kenneth... | update rotator.py to match microwatt rotator.vhdl |
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2020-06-07 |
Luke Kenneth... | add carry test to shift_rot test_pipe_caller: it fails... |
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2020-06-07 |
Luke Kenneth... | add extra args to ISA in test_pipe_caller.py |
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2020-06-07 |
Luke Kenneth... | add make clean target to qemu_test Makefile |
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2020-06-07 |
Luke Kenneth... | optionally writing out CA/CA32 to XER |
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2020-06-07 |
Luke Kenneth... | add handling of CA/CA32 in simulator, generated from... |
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2020-06-07 |
Luke Kenneth... | add CA/CA32 to list of special regs |
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2020-06-07 |
Luke Kenneth... | add missing arg to ISA in test_compunit |
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2020-06-07 |
Luke Kenneth... | Revert "if referred to through GPR (GPR[RA]), add to... |
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2020-06-07 |
Luke Kenneth... | Revert "remove fixedlogical.patch - added gprs to Power... |
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2020-06-07 |
Luke Kenneth... | Revert "add gprs to PowerParser write_regs in p_atom_name" |
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2020-06-07 |
Luke Kenneth... | add extra missing args to ISA setup in alu test_pipe_caller |
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2020-06-07 |
Luke Kenneth... | if referred to through GPR (GPR[RA]), add to read_regs... |
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2020-06-07 |
Luke Kenneth... | add gprs to PowerParser write_regs in p_atom_name |
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2020-06-07 |
Luke Kenneth... | add missing args to ISA |
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2020-06-07 |
Luke Kenneth... | remove fixedlogical.patch - added gprs to PowerParser... |
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2020-06-07 |
Luke Kenneth... | docstring on caller.py inject() decorator |
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2020-06-07 |
Luke Kenneth... | add TRAP function, stub |
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2020-06-07 |
Luke Kenneth... | update submodule for sprset.mdwn |
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2020-06-07 |
Luke Kenneth... | add MSR to simulator context |
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2020-06-07 |
Luke Kenneth... | move MSR_PR checking to separate functiong |
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2020-06-07 |
colepoirier | Fix missing 'comb +=' |
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2020-06-06 |
Luke Kenneth... | add python3 env-var if not set in Makefile |
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2020-06-06 |
Luke Kenneth... | experimenting with setting up and testing memory |
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2020-06-06 |
Luke Kenneth... | expand regwid to 64 in l0_cache test |
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2020-06-06 |
Luke Kenneth... | work out how to initialise memory directly |
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2020-06-06 |
Luke Kenneth... | initialise L0 Memory from simulator memory |
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2020-06-06 |
Luke Kenneth... | wait a little for wr.rel to activate if wrmask is active |
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2020-06-06 |
Luke Kenneth... | missing test.mem arg for ISA in test_core |
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2020-06-06 |
Luke Kenneth... | allow Mem initialisation in ISACaller |
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2020-06-06 |
Luke Kenneth... | shift-mask in Simulator Mem class not quite right |
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2020-06-06 |
Luke Kenneth... | write-mask made from LD and Update mode (for data_o... |
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2020-06-06 |
Luke Kenneth... | allow Mem in Simulator to be initialised |
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2020-06-06 |
Luke Kenneth... | use name of unit to write simulator/vcd file |
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2020-06-06 |
Luke Kenneth... | LDSTCompUnit test data structures linked up, starting... |
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2020-06-06 |
Luke Kenneth... | allow CompLDSTOpSubset to be passed through to LDSTCompUnit |
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2020-06-06 |
Luke Kenneth... | set up LDSTCompUnit using regspec |
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2020-06-06 |
Luke Kenneth... | add extra bugreport link |
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2020-06-06 |
Luke Kenneth... | whitespace |
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2020-06-06 |
Luke Kenneth... | whitespace indentation |
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2020-06-06 |
Luke Kenneth... | add special-case LDSTFunctionUnit |
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2020-06-06 |
Luke Kenneth... | whoops dest%d_o not dest%d_i |
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2020-06-06 |
Luke Kenneth... | add beginnings of LDST compunit test |
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2020-06-06 |
Luke Kenneth... | whitespace |
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2020-06-06 |
Luke Kenneth... | whitespace / code-munge |
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2020-06-06 |
Luke Kenneth... | comments / whitespace |
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2020-06-06 |
Luke Kenneth... | update stage docstring |
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2020-06-06 |
Luke Kenneth... | code-munge |
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2020-06-06 |
Luke Kenneth... | remove unneeded imports |
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2020-06-06 |
Luke Kenneth... | noticed the regular pattern in all pipe_data.py (regspecs). |
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