2020-03-14 |
Jock Tanner | Delete stale code. |
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2020-03-13 |
Jock Tanner | Fix style, imports, stale code. |
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2020-03-13 |
Jock Tanner | Add experiment #7. |
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2020-03-06 |
Luke Kenneth... | add ioring.py (forgot about) |
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2020-03-06 |
lkcl | whoops removed mksym.sh when shouldnt |
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2020-03-06 |
lkcl | interesting: using nsxlib in experiment/ never terminates |
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2020-03-06 |
lkcl | experiment2 experimentation... |
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2020-03-06 |
lkcl | remove mksym.sh from low-level |
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2020-03-04 |
Luke Kenneth... | add cmos to mksym.sh, disable YOSYS_FLATTEN |
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2020-03-04 |
Jean-Paul Chaput | Correct configuration for fpmul64. |
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2020-03-02 |
Luke Kenneth... | add fpmul64.il test, to see how long it takes (10 minut... |
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2020-03-01 |
Luke Kenneth... | managed to hack something together to get alu_hier... |
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2020-02-28 |
Luke Kenneth... | add alu_hier place/route, partially works |
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2020-02-28 |
Luke Kenneth... | add sub function (class-ish form) |
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2020-02-28 |
Luke Kenneth... | successful ring created around add.ap |
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2020-02-28 |
Luke Kenneth... | hmm still not adding traces |
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2020-02-28 |
Luke Kenneth... | add VIA but metal not working yet |
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2020-02-28 |
Luke Kenneth... | move add and sub, shrink alu_hier box |
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2020-02-27 |
Luke Kenneth... | place and route alu_hier, not quite working yet |
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2020-02-27 |
Luke Kenneth... | do sub layout as well |
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2020-02-27 |
Luke Kenneth... | "UnManaged Configuration [16843009] = [1+1+0+1,1+0... |
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2020-02-27 |
Luke Kenneth... | try adding short track manually (doesnt work) |
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2020-02-27 |
Luke Kenneth... | getting closer to connecting at edge |
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2020-02-27 |
Luke Kenneth... | successful route but still 40L off the top |
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2020-02-27 |
Luke Kenneth... | overlap error in routing (two connections on same... |
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2020-02-26 |
Luke Kenneth... | more experimenting, got cell down to smallest size... |
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2020-02-26 |
Luke Kenneth... | segfault in pyDoAlu16.py |
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2020-02-26 |
Luke Kenneth... | experiment with subtractor |
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2020-02-25 |
Luke Kenneth... | add first experimental hierarchical place/route |
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2020-02-25 |
Luke Kenneth... | add experiment5 |
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2020-02-25 |
Luke Kenneth... | add clk and ck so that ck is recognised for routing |
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2020-02-24 |
Luke Kenneth... | add make view |
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2020-02-24 |
Luke Kenneth... | bit more experimenting making an ioring around an adder |
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2020-02-24 |
Luke Kenneth... | make example as close to adder benchmark as possible |
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2020-02-24 |
Luke Kenneth... | simplify experiment4 to an adder, similar to adder... |
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2020-02-24 |
Luke Kenneth... | add mksyms.sh |
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2020-02-24 |
Luke Kenneth... | whoops yes use clocktree |
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2020-02-24 |
Luke Kenneth... | add missing mksym.sh |
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2020-02-24 |
Luke Kenneth... | continue experimentation |
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2020-02-23 |
Luke Kenneth... | add sm3 to nets |
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2020-02-22 |
Luke Kenneth... | correct nets for experiment2 |
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2020-02-22 |
Luke Kenneth... | track down module in which vdd / vss error exists ... |
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2020-02-22 |
Luke Kenneth... | remove working code, shrink "fail" case |
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2020-02-22 |
Luke Kenneth... | add test_partsig.py directly to experiment2 |
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2020-02-22 |
Luke Kenneth... | add ioring experiment |
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2020-02-22 |
Luke Kenneth... | add sim just to see if anything happens |
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2020-02-22 |
Luke Kenneth... | move Makefile3/4 to experiments3 |
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2020-02-22 |
Luke Kenneth... | move part_sig_add to its own directory |
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2020-02-22 |
Luke Kenneth... | move alu_hier to own directory |
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2020-02-22 |
Luke Kenneth... | change coriolis settings, logmode true |
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2020-02-21 |
Luke Kenneth... | add extra gitignores |
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2020-02-21 |
Luke Kenneth... | add path helpers sys libraries |
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2020-02-21 |
Luke Kenneth... | add git ignore file |
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2020-02-21 |
Luke Kenneth... | wrong script name |
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2020-02-21 |
Luke Kenneth... | remove synthesise-yosys.mk use alliance one |
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2020-02-21 |
Luke Kenneth... | add GND/PWR to see what happens in settings.py |
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2020-02-21 |
Luke Kenneth... | reduce pmask to stop unconnected bits |
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2020-02-21 |
Luke Kenneth... | use alternative experimental class TestAddMod2 |
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2020-02-20 |
Luke Kenneth... | fix mask width |
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2020-02-20 |
Luke Kenneth... | add Makefile3 |
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2020-02-20 |
Luke Kenneth... | add second Makefile |
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2020-02-20 |
Luke Kenneth... | move part_sig_add name |
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2020-02-20 |
Luke Kenneth... | run alu_hier.py instead of alu.py (works) |
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2020-02-20 |
Luke Kenneth... | remove clock |
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2020-02-19 |
Luke Kenneth... | remove clock, use rename on clk in settings |
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2020-02-19 |
Luke Kenneth... | increase etesian, set clock to clk |
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2020-02-19 |
Luke Kenneth... | use simpler alu rather than alu_hier |
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2020-02-19 |
Luke Kenneth... | add clocks and reset and add alu.py as well |
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2020-02-19 |
Luke Kenneth... | replace part_sig_add with simpler design |
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2020-02-19 |
Luke Kenneth... | add alu_hier.py example |
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2020-02-19 |
Luke Kenneth... | replace VLOG with ILANG |
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2020-02-19 |
Luke Kenneth... | start running and debugging |
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2020-02-19 |
Luke Kenneth... | try symlink to mk fragments |
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2020-02-15 |
Luke Kenneth... | remove whitespace |
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2020-02-15 |
Tobias Platen | yosys example makefile |
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2020-02-14 |
Luke Kenneth... | add synthesis-yosys.mk with ilang substituted |
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2020-02-14 |
Tobias Platen | first example code |
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2020-02-11 |
Luke Kenneth... | first empty commit |
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