src/ieee754/add/test_fpnum.py

   1 from random import randint
   2 from nmigen import Module, Signal
   3 from nmigen.compat.sim import run_simulation
   4
   5 from ieee754.fpcommon.fpbase import FPNum
   6
   7 class FPNumModShiftMulti:
   8     def __init__(self, width):
   9         self.a = FPNum(width)
  10         self.ediff = Signal((self.a.e_width, True))
  11
  12     def elaborate(self, platform=None):
  13
  14         m = Module()
  15         #m.d.sync += self.a.decode(self.a.v)
  16         m.d.sync += self.a.shift_down_multi(self.ediff)
  17
  18         return m
  19
  20 def check_case(dut, width, e_width, m, e, i):
  21     yield dut.a.m.eq(m)
  22     yield dut.a.e.eq(e)
  23     yield dut.ediff.eq(i)
  24     yield
  25     yield
  26
  27     out_m = yield dut.a.m
  28     out_e = yield dut.a.e
  29     ed = yield dut.ediff
  30     calc_e = (e + i)
  31     print (e, bin(m), out_e, calc_e, bin(out_m), i, ed)
  32
  33     calc_m = ((m >> (i+1)) << 1) | (m & 1)
  34     for l in range(i):
  35         if m & (1<<(l+1)):
  36             calc_m |= 1
  37
  38     assert out_e == calc_e, "Output e 0x%x != expected 0x%x" % (out_e, calc_e)
  39     assert out_m == calc_m, "Output m 0x%x != expected 0x%x" % (out_m, calc_m)
  40
  41 def testbench(dut):
  42     m_width = dut.a.m_width
  43     e_width = dut.a.e_width
  44     e_max = dut.a.e_max
  45     for j in range(200):
  46         m = randint(0, (1<<m_width)-1)
  47         zeros = randint(0, 31)
  48         for i in range(zeros):
  49             m &= ~(1<<i)
  50         e = randint(-e_max, e_max)
  51         for i in range(32):
  52             yield from check_case(dut, m_width, e_width, m, e, i)
  53
  54 if __name__ == '__main__':
  55     dut = FPNumModShiftMulti(width=32)
  56     run_simulation(dut, testbench(dut), vcd_name="test_multishift.vcd")
  57
  58     #dut = MultiShiftModL(width=32)
  59     #run_simulation(dut, testbench(dut), vcd_name="test_multishift.vcd")
  60