src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  22 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  23 from ieee754.part_mul_add.partpoints import make_partition, PartitionPoints
  24 from operator import or_, xor, and_, not_
  25
  26 from nmigen import (Signal, Const)
  27
  28
  29 def getsig(op1):
  30     if isinstance(op1, PartitionedSignal):
  31         op1 = op1.sig
  32     return op1
  33
  34
  35 def applyop(op1, op2, op):
  36     return op(getsig(op1), getsig(op2))
  37
  38
  39 class PartitionedSignal:
  40     def __init__(self, mask, *args, **kwargs):
  41         self.sig = Signal(*args, **kwargs)
  42         width = len(self.sig)  # get signal width
  43         # create partition points
  44         if isinstance(mask, PartitionPoints):
  45             self.partpoints = mask
  46         else:
  47             self.partpoints = make_partition(mask, width)
  48         self.modnames = {}
  49         for name in ['add', 'eq', 'gt', 'ge', 'ls']:
  50             self.modnames[name] = 0
  51
  52     def set_module(self, m):
  53         self.m = m
  54
  55     def get_modname(self, category):
  56         self.modnames[category] += 1
  57         return "%s_%d" % (category, self.modnames[category])
  58
  59     def eq(self, val):
  60         return self.sig.eq(getsig(val))
  61
  62     # unary ops that do not require partitioning
  63
  64     def __invert__(self):
  65         return ~self.sig
  66
  67     # unary ops that require partitioning
  68
  69     def __neg__(self):
  70         z = Const(0, len(self.partpoints)+1)
  71         result, _ = self.add_op(self, ~0, carry=z)  # TODO, subop
  72         return result
  73
  74     # binary ops that don't require partitioning
  75
  76     def __and__(self, other):
  77         return applyop(self, other, and_)
  78
  79     def __rand__(self, other):
  80         return applyop(other, self, and_)
  81
  82     def __or__(self, other):
  83         return applyop(self, other, or_)
  84
  85     def __ror__(self, other):
  86         return applyop(other, self, or_)
  87
  88     def __xor__(self, other):
  89         return applyop(self, other, xor)
  90
  91     def __rxor__(self, other):
  92         return applyop(other, self, xor)
  93
  94     # binary ops that need partitioning
  95
  96     # TODO: detect if the 2nd operand is a Const, a Signal or a
  97     # PartitionedSignal.  if it's a Const or a Signal, a global shift
  98     # can occur.  if it's a PartitionedSignal, that's much more interesting.
  99     def ls_op(self, op1, op2, carry, shr_flag=0):
 100         op1 = getsig(op1)
 101         if isinstance(op2, Const) or isinstance(op2, Signal):
 102             scalar = True
 103             pa = PartitionedScalarShift(len(op1), self.partpoints)
 104         else:
 105             scalar = False
 106             op2 = getsig(op2)
 107             pa = PartitionedDynamicShift(len(op1), self.partpoints)
 108         setattr(self.m.submodules, self.get_modname('ls'), pa)
 109         comb = self.m.d.comb
 110         if scalar:
 111             comb += pa.data.eq(op1)
 112             comb += pa.shifter.eq(op2)
 113             comb += pa.shift_right.eq(shr_flag)
 114         else:
 115             comb += pa.a.eq(op1)
 116             comb += pa.b.eq(op2)
 117             comb += pa.shift_right.eq(shr_flag)
 118         # XXX TODO: carry-in, carry-out
 119         #comb += pa.carry_in.eq(carry)
 120         return (pa.output, 0)
 121
 122     def __lshift__(self, other):
 123         z = Const(0, len(self.partpoints)+1)
 124         result, _ = self.ls_op(self, other, carry=z) # TODO, carry
 125         return result
 126
 127     def __rlshift__(self, other):
 128         raise NotImplementedError
 129         return Operator("<<", [other, self])
 130
 131     def __rshift__(self, other):
 132         z = Const(0, len(self.partpoints)+1)
 133         result, _ = self.ls_op(self, other, carry=z, shr_flag=1) # TODO, carry
 134         return result
 135
 136     def __rrshift__(self, other):
 137         raise NotImplementedError
 138         return Operator(">>", [other, self])
 139
 140     def add_op(self, op1, op2, carry):
 141         op1 = getsig(op1)
 142         op2 = getsig(op2)
 143         pa = PartitionedAdder(len(op1), self.partpoints)
 144         setattr(self.m.submodules, self.get_modname('add'), pa)
 145         comb = self.m.d.comb
 146         comb += pa.a.eq(op1)
 147         comb += pa.b.eq(op2)
 148         comb += pa.carry_in.eq(carry)
 149         return (pa.output, pa.carry_out)
 150
 151     def sub_op(self, op1, op2, carry=~0):
 152         op1 = getsig(op1)
 153         op2 = getsig(op2)
 154         pa = PartitionedAdder(len(op1), self.partpoints)
 155         setattr(self.m.submodules, self.get_modname('add'), pa)
 156         comb = self.m.d.comb
 157         comb += pa.a.eq(op1)
 158         comb += pa.b.eq(~op2)
 159         comb += pa.carry_in.eq(carry)
 160         return (pa.output, pa.carry_out)
 161
 162     def __add__(self, other):
 163         result, _ = self.add_op(self, other, carry=0)
 164         return result
 165
 166     def __radd__(self, other):
 167         result, _ = self.add_op(other, self)
 168         return result
 169
 170     def __sub__(self, other):
 171         result, _ = self.sub_op(self, other)
 172         return result
 173
 174     def __rsub__(self, other):
 175         result, _ = self.sub_op(other, self)
 176         return result
 177
 178     def __mul__(self, other):
 179         return Operator("*", [self, other])
 180
 181     def __rmul__(self, other):
 182         return Operator("*", [other, self])
 183
 184     def __check_divisor(self):
 185         width, signed = self.shape()
 186         if signed:
 187             # Python's division semantics and Verilog's division semantics
 188             # differ for negative divisors (Python uses div/mod, Verilog
 189             # uses quo/rem); for now, avoid the issue
 190             # completely by prohibiting such division operations.
 191             raise NotImplementedError(
 192                     "Division by a signed value is not supported")
 193
 194     def __mod__(self, other):
 195         raise NotImplementedError
 196         other = Value.cast(other)
 197         other.__check_divisor()
 198         return Operator("%", [self, other])
 199
 200     def __rmod__(self, other):
 201         raise NotImplementedError
 202         self.__check_divisor()
 203         return Operator("%", [other, self])
 204
 205     def __floordiv__(self, other):
 206         raise NotImplementedError
 207         other = Value.cast(other)
 208         other.__check_divisor()
 209         return Operator("//", [self, other])
 210
 211     def __rfloordiv__(self, other):
 212         raise NotImplementedError
 213         self.__check_divisor()
 214         return Operator("//", [other, self])
 215
 216     # binary comparison ops that need partitioning
 217
 218     def _compare(self, width, op1, op2, opname, optype):
 219         # print (opname, op1, op2)
 220         pa = PartitionedEqGtGe(width, self.partpoints)
 221         setattr(self.m.submodules, self.get_modname(opname), pa)
 222         comb = self.m.d.comb
 223         comb += pa.opcode.eq(optype)  # set opcode
 224         if isinstance(op1, PartitionedSignal):
 225             comb += pa.a.eq(op1.sig)
 226         else:
 227             comb += pa.a.eq(op1)
 228         if isinstance(op2, PartitionedSignal):
 229             comb += pa.b.eq(op2.sig)
 230         else:
 231             comb += pa.b.eq(op2)
 232         return pa.output
 233
 234     def __eq__(self, other):
 235         width = len(self.sig)
 236         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 237
 238     def __ne__(self, other):
 239         width = len(self.sig)
 240         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 241         ne = Signal(eq.width)
 242         self.m.d.comb += ne.eq(~eq)
 243         return ne
 244
 245     def __gt__(self, other):
 246         width = len(self.sig)
 247         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 248
 249     def __lt__(self, other):
 250         width = len(self.sig)
 251         # swap operands, use gt to do lt
 252         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 253
 254     def __ge__(self, other):
 255         width = len(self.sig)
 256         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 257
 258     def __le__(self, other):
 259         width = len(self.sig)
 260         # swap operands, use ge to do le
 261         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 262
 263     # useful operators
 264
 265     def bool(self):
 266         """Conversion to boolean.
 267
 268         Returns
 269         -------
 270         Value, out
 271             ``1`` if any bits are set, ``0`` otherwise.
 272         """
 273         return self.any() # have to see how this goes
 274         #return Operator("b", [self])
 275
 276     def any(self):
 277         """Check if any bits are ``1``.
 278
 279         Returns
 280         -------
 281         Value, out
 282             ``1`` if any bits are set, ``0`` otherwise.
 283         """
 284         return Operator("r|", [self])
 285
 286     def all(self):
 287         """Check if all bits are ``1``.
 288
 289         Returns
 290         -------
 291         Value, out
 292             ``1`` if all bits are set, ``0`` otherwise.
 293         """
 294         return self == Const(-1) # leverage the __eq__ operator here
 295
 296     def xor(self):
 297         """Compute pairwise exclusive-or of every bit.
 298
 299         Returns
 300         -------
 301         Value, out
 302             ``1`` if an odd number of bits are set, ``0`` if an
 303                   even number of bits are set.
 304         """
 305         # XXXX TODO: return partition-mask-sized set of bits
 306         raise NotImplementedError
 307         return Operator("r^", [self])
 308
 309     def implies(premise, conclusion):
 310         """Implication.
 311
 312         Returns
 313         -------
 314         Value, out
 315             ``0`` if ``premise`` is true and ``conclusion`` is not,
 316             ``1`` otherwise.
 317         """
 318         # amazingly, this should actually work.
 319         return ~premise | conclusion