src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use SimdSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_bits.xor import PartitionedXOR
  22 from ieee754.part_bits.bool import PartitionedBool
  23 from ieee754.part_bits.all import PartitionedAll
  24 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  25 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  26 from ieee754.part_mul_add.partpoints import make_partition2, PartitionPoints
  27 from ieee754.part_mux.part_mux import PMux
  28 from ieee754.part_ass.passign import PAssign
  29 from ieee754.part_cat.pcat import PCat
  30 from ieee754.part_repl.prepl import PRepl
  31 from operator import or_, xor, and_, not_
  32
  33 from nmigen import (Signal, Const, Cat)
  34 from nmigen.hdl.ast import UserValue, Shape
  35
  36
  37 def getsig(op1):
  38     if isinstance(op1, SimdSignal):
  39         op1 = op1.sig
  40     return op1
  41
  42
  43 def applyop(op1, op2, op):
  44     if isinstance(op1, SimdSignal):
  45         result = SimdSignal.like(op1)
  46     else:
  47         result = SimdSignal.like(op2)
  48     result.m.d.comb += result.sig.eq(op(getsig(op1), getsig(op2)))
  49     return result
  50
  51
  52 global modnames
  53 modnames = {}
  54 # for sub-modules to be created on-demand. Mux is done slightly
  55 # differently (has its own global)
  56 for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor', 'bool', 'all']:
  57     modnames[name] = 0
  58
  59
  60 # Prototype https://bugs.libre-soc.org/show_bug.cgi?id=713#c53
  61 # this provides a "compatibility" layer with existing SimdSignal
  62 # behaviour.  the idea is that this interface defines which "combinations"
  63 # of partition selections are relevant, and as an added bonus it says
  64 # which partition lanes are completely irrelevant (padding, blank).
  65 class PartType:  # TODO decide name
  66     def __init__(self, psig):
  67         self.psig = psig
  68
  69     def get_mask(self):
  70         return list(self.psig.partpoints.values())
  71
  72     def get_switch(self):
  73         return Cat(self.get_mask())
  74
  75     def get_cases(self):
  76         return range(1 << len(self.get_mask()))
  77
  78     @property
  79     def blanklanes(self):
  80         return 0
  81
  82 # this one would be an elwidth version
  83 # see https://bugs.libre-soc.org/show_bug.cgi?id=713#c34
  84 # it requires an "adapter" which is the layout() function
  85 # where the PartitionPoints was *created* by the layout()
  86 # function and this class then "understands" the relationship
  87 # between elwidth and the PartitionPoints that were created
  88 # by layout()
  89
  90
  91 class ElWidthPartType:  # TODO decide name
  92     def __init__(self, psig):
  93         self.psig = psig
  94
  95     def get_mask(self):
  96         ppoints, pbits = layout()
  97         return ppoints.values()  # i think
  98
  99     def get_switch(self):
 100         return self.psig.elwidth
 101
 102     def get_cases(self):
 103         ppoints, pbits = layout()
 104         return pbits
 105
 106     @property
 107     def blanklanes(self):
 108         return 0  # TODO
 109
 110
 111 class SimdSignal(UserValue):
 112     # XXX ################################################### XXX
 113     # XXX Keep these functions in the same order as ast.Value XXX
 114     # XXX ################################################### XXX
 115     def __init__(self, mask, *args, src_loc_at=0, **kwargs):
 116         super().__init__(src_loc_at=src_loc_at)
 117         self.sig = Signal(*args, **kwargs)
 118         width = len(self.sig)  # get signal width
 119         # create partition points
 120         if isinstance(mask, PartitionPoints):
 121             self.partpoints = mask
 122         else:
 123             self.partpoints = make_partition2(mask, width)
 124         self.ptype = PartType(self)
 125
 126     def set_module(self, m):
 127         self.m = m
 128
 129     def get_modname(self, category):
 130         modnames[category] += 1
 131         return "%s_%d" % (category, modnames[category])
 132
 133     @staticmethod
 134     def like(other, *args, **kwargs):
 135         """Builds a new SimdSignal with the same PartitionPoints and
 136         Signal properties as the other"""
 137         result = SimdSignal(PartitionPoints(other.partpoints))
 138         result.sig = Signal.like(other.sig, *args, **kwargs)
 139         result.m = other.m
 140         return result
 141
 142     def lower(self):
 143         return self.sig
 144
 145     # nmigen-redirected constructs (Mux, Cat, Switch, Assign)
 146
 147     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 148     #def __Part__(self, offset, width, stride=1, *, src_loc_at=0):
 149         raise NotImplementedError("TODO: implement as "
 150                         "(self>>(offset*stride)[:width]")
 151     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 152     def __Slice__(self, start, stop, *, src_loc_at=0):
 153         # NO.  Swizzled shall NOT be deployed, it violates
 154         # Project Development Practices
 155         raise NotImplementedError("TODO: need PartitionedSlice")
 156
 157     def __Repl__(self, count, *, src_loc_at=0):
 158         return PRepl(self.m, self, count, self.ptype)
 159
 160     def __Cat__(self, *args, src_loc_at=0):
 161         print ("partsig cat", self, args)
 162         # TODO: need SwizzledSimdValue-aware Cat
 163         args = [self] + list(args)
 164         for sig in args:
 165             assert isinstance(sig, SimdSignal), \
 166                 "All SimdSignal.__Cat__ arguments must be " \
 167                 "a SimdSignal. %s is not." % repr(sig)
 168         return PCat(self.m, args, self.ptype)
 169
 170     def __Mux__(self, val1, val2):
 171         # print ("partsig mux", self, val1, val2)
 172         assert len(val1) == len(val2), \
 173             "SimdSignal width sources must be the same " \
 174             "val1 == %d, val2 == %d" % (len(val1), len(val2))
 175         return PMux(self.m, self.partpoints, self, val1, val2, self.ptype)
 176
 177     def __Assign__(self, val, *, src_loc_at=0):
 178         print ("partsig assign", self, val)
 179         # this is a truly awful hack, outlined here:
 180         # https://bugs.libre-soc.org/show_bug.cgi?id=731#c13
 181         # during the period between constructing Simd-aware sub-modules
 182         # and the elaborate() being called on them there is a window of
 183         # opportunity to indicate which of those submodules is LHS and
 184         # which is RHS. manic laughter is permitted.  *gibber*.
 185         if hasattr(self, "_hack_submodule"):
 186             self._hack_submodule.set_lhs_mode(True)
 187         if hasattr(val, "_hack_submodule"):
 188             val._hack_submodule.set_lhs_mode(False)
 189         return PAssign(self.m, self, val, self.ptype)
 190
 191     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=458
 192     # def __Switch__(self, cases, *, src_loc=None, src_loc_at=0,
 193     #                               case_src_locs={}):
 194
 195     # no override needed, Value.__bool__ sufficient
 196     # def __bool__(self):
 197
 198     # unary ops that do not require partitioning
 199
 200     def __invert__(self):
 201         result = SimdSignal.like(self)
 202         self.m.d.comb += result.sig.eq(~self.sig)
 203         return result
 204
 205     # unary ops that require partitioning
 206
 207     def __neg__(self):
 208         z = Const(0, len(self.sig))
 209         result, _ = self.sub_op(z, self)
 210         return result
 211
 212     # binary ops that need partitioning
 213
 214     def add_op(self, op1, op2, carry):
 215         op1 = getsig(op1)
 216         op2 = getsig(op2)
 217         pa = PartitionedAdder(len(op1), self.partpoints)
 218         setattr(self.m.submodules, self.get_modname('add'), pa)
 219         comb = self.m.d.comb
 220         comb += pa.a.eq(op1)
 221         comb += pa.b.eq(op2)
 222         comb += pa.carry_in.eq(carry)
 223         result = SimdSignal.like(self)
 224         comb += result.sig.eq(pa.output)
 225         return result, pa.carry_out
 226
 227     def sub_op(self, op1, op2, carry=~0):
 228         op1 = getsig(op1)
 229         op2 = getsig(op2)
 230         pa = PartitionedAdder(len(op1), self.partpoints)
 231         setattr(self.m.submodules, self.get_modname('add'), pa)
 232         comb = self.m.d.comb
 233         comb += pa.a.eq(op1)
 234         comb += pa.b.eq(~op2)
 235         comb += pa.carry_in.eq(carry)
 236         result = SimdSignal.like(self)
 237         comb += result.sig.eq(pa.output)
 238         return result, pa.carry_out
 239
 240     def __add__(self, other):
 241         result, _ = self.add_op(self, other, carry=0)
 242         return result
 243
 244     def __radd__(self, other):
 245         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 246         result, _ = self.add_op(other, self)
 247         return result
 248
 249     def __sub__(self, other):
 250         result, _ = self.sub_op(self, other)
 251         return result
 252
 253     def __rsub__(self, other):
 254         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 255         result, _ = self.sub_op(other, self)
 256         return result
 257
 258     def __mul__(self, other):
 259         raise NotImplementedError  # too complicated at the moment
 260         return Operator("*", [self, other])
 261
 262     def __rmul__(self, other):
 263         raise NotImplementedError  # too complicated at the moment
 264         return Operator("*", [other, self])
 265
 266     # not needed: same as Value.__check_divisor
 267     # def __check_divisor(self):
 268
 269     def __mod__(self, other):
 270         raise NotImplementedError
 271         other = Value.cast(other)
 272         other.__check_divisor()
 273         return Operator("%", [self, other])
 274
 275     def __rmod__(self, other):
 276         raise NotImplementedError
 277         self.__check_divisor()
 278         return Operator("%", [other, self])
 279
 280     def __floordiv__(self, other):
 281         raise NotImplementedError
 282         other = Value.cast(other)
 283         other.__check_divisor()
 284         return Operator("//", [self, other])
 285
 286     def __rfloordiv__(self, other):
 287         raise NotImplementedError
 288         self.__check_divisor()
 289         return Operator("//", [other, self])
 290
 291     # not needed: same as Value.__check_shamt
 292     # def __check_shamt(self):
 293
 294     # TODO: detect if the 2nd operand is a Const, a Signal or a
 295     # SimdSignal.  if it's a Const or a Signal, a global shift
 296     # can occur.  if it's a SimdSignal, that's much more interesting.
 297     def ls_op(self, op1, op2, carry, shr_flag=0):
 298         op1 = getsig(op1)
 299         if isinstance(op2, Const) or isinstance(op2, Signal):
 300             scalar = True
 301             pa = PartitionedScalarShift(len(op1), self.partpoints)
 302         else:
 303             scalar = False
 304             op2 = getsig(op2)
 305             pa = PartitionedDynamicShift(len(op1), self.partpoints)
 306         # else:
 307         #   TODO: case where the *shifter* is a SimdSignal but
 308         #   the thing *being* Shifted is a scalar (Signal, expression)
 309         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 310         setattr(self.m.submodules, self.get_modname('ls'), pa)
 311         comb = self.m.d.comb
 312         if scalar:
 313             comb += pa.data.eq(op1)
 314             comb += pa.shifter.eq(op2)
 315             comb += pa.shift_right.eq(shr_flag)
 316         else:
 317             comb += pa.a.eq(op1)
 318             comb += pa.b.eq(op2)
 319             comb += pa.shift_right.eq(shr_flag)
 320         # XXX TODO: carry-in, carry-out (for arithmetic shift)
 321         #comb += pa.carry_in.eq(carry)
 322         return (pa.output, 0)
 323
 324     def __lshift__(self, other):
 325         z = Const(0, len(self.partpoints)+1)
 326         result, _ = self.ls_op(self, other, carry=z)  # TODO, carry
 327         return result
 328
 329     def __rlshift__(self, other):
 330         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 331         raise NotImplementedError
 332         return Operator("<<", [other, self])
 333
 334     def __rshift__(self, other):
 335         z = Const(0, len(self.partpoints)+1)
 336         result, _ = self.ls_op(self, other, carry=z, shr_flag=1)  # TODO, carry
 337         return result
 338
 339     def __rrshift__(self, other):
 340         #   https://bugs.libre-soc.org/show_bug.cgi?id=718
 341         raise NotImplementedError
 342         return Operator(">>", [other, self])
 343
 344     # binary ops that don't require partitioning
 345
 346     def __and__(self, other):
 347         return applyop(self, other, and_)
 348
 349     def __rand__(self, other):
 350         return applyop(other, self, and_)
 351
 352     def __or__(self, other):
 353         return applyop(self, other, or_)
 354
 355     def __ror__(self, other):
 356         return applyop(other, self, or_)
 357
 358     def __xor__(self, other):
 359         return applyop(self, other, xor)
 360
 361     def __rxor__(self, other):
 362         return applyop(other, self, xor)
 363
 364     # binary comparison ops that need partitioning
 365
 366     def _compare(self, width, op1, op2, opname, optype):
 367         # print (opname, op1, op2)
 368         pa = PartitionedEqGtGe(width, self.partpoints)
 369         setattr(self.m.submodules, self.get_modname(opname), pa)
 370         comb = self.m.d.comb
 371         comb += pa.opcode.eq(optype)  # set opcode
 372         if isinstance(op1, SimdSignal):
 373             comb += pa.a.eq(op1.sig)
 374         else:
 375             comb += pa.a.eq(op1)
 376         if isinstance(op2, SimdSignal):
 377             comb += pa.b.eq(op2.sig)
 378         else:
 379             comb += pa.b.eq(op2)
 380         return pa.output
 381
 382     def __eq__(self, other):
 383         width = len(self.sig)
 384         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 385
 386     def __ne__(self, other):
 387         width = len(self.sig)
 388         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 389         ne = Signal(eq.width)
 390         self.m.d.comb += ne.eq(~eq)
 391         return ne
 392
 393     def __lt__(self, other):
 394         width = len(self.sig)
 395         # swap operands, use gt to do lt
 396         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 397
 398     def __le__(self, other):
 399         width = len(self.sig)
 400         # swap operands, use ge to do le
 401         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 402
 403     def __gt__(self, other):
 404         width = len(self.sig)
 405         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 406
 407     def __ge__(self, other):
 408         width = len(self.sig)
 409         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 410
 411     # no override needed: Value.__abs__ is general enough it does the job
 412     # def __abs__(self):
 413
 414     def __len__(self):
 415         return len(self.sig)
 416
 417     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=716
 418     # def __getitem__(self, key):
 419
 420     def __new_sign(self, signed):
 421         shape = Shape(len(self), signed=signed)
 422         result = SimdSignal.like(self, shape=shape)
 423         self.m.d.comb += result.sig.eq(self.sig)
 424         return result
 425
 426     # http://bugs.libre-riscv.org/show_bug.cgi?id=719
 427     def as_unsigned(self):
 428         return self.__new_sign(False)
 429
 430     def as_signed(self):
 431         return self.__new_sign(True)
 432
 433     # useful operators
 434
 435     def bool(self):
 436         """Conversion to boolean.
 437
 438         Returns
 439         -------
 440         Value, out
 441             ``1`` if any bits are set, ``0`` otherwise.
 442         """
 443         width = len(self.sig)
 444         pa = PartitionedBool(width, self.partpoints)
 445         setattr(self.m.submodules, self.get_modname("bool"), pa)
 446         self.m.d.comb += pa.a.eq(self.sig)
 447         return pa.output
 448
 449     def any(self):
 450         """Check if any bits are ``1``.
 451
 452         Returns
 453         -------
 454         Value, out
 455             ``1`` if any bits are set, ``0`` otherwise.
 456         """
 457         return self != Const(0)  # leverage the __ne__ operator here
 458         return Operator("r|", [self])
 459
 460     def all(self):
 461         """Check if all bits are ``1``.
 462
 463         Returns
 464         -------
 465         Value, out
 466             ``1`` if all bits are set, ``0`` otherwise.
 467         """
 468         # something wrong with PartitionedAll, but self == Const(-1)"
 469         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=176#c17
 470         #width = len(self.sig)
 471         #pa = PartitionedAll(width, self.partpoints)
 472         #setattr(self.m.submodules, self.get_modname("all"), pa)
 473         #self.m.d.comb += pa.a.eq(self.sig)
 474         # return pa.output
 475         return self == Const(-1)  # leverage the __eq__ operator here
 476
 477     def xor(self):
 478         """Compute pairwise exclusive-or of every bit.
 479
 480         Returns
 481         -------
 482         Value, out
 483             ``1`` if an odd number of bits are set, ``0`` if an
 484                   even number of bits are set.
 485         """
 486         width = len(self.sig)
 487         pa = PartitionedXOR(width, self.partpoints)
 488         setattr(self.m.submodules, self.get_modname("xor"), pa)
 489         self.m.d.comb += pa.a.eq(self.sig)
 490         return pa.output
 491
 492     # not needed: Value.implies does the job
 493     # def implies(premise, conclusion):
 494
 495     # TODO. contains a Value.cast which means an override is needed (on both)
 496     # def bit_select(self, offset, width):
 497     # def word_select(self, offset, width):
 498
 499     # not needed: Value.matches, amazingly, should do the job
 500     # def matches(self, *patterns):
 501
 502     # TODO, http://bugs.libre-riscv.org/show_bug.cgi?id=713
 503     def shape(self):
 504         return self.sig.shape()