src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
  21 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal,
  26                     )
  27 def applyop(op1, op2, op):
  28     if isinstance(op1, PartitionedSignal):
  29         op1 = op1.sig
  30     if isinstance(op2, PartitionedSignal):
  31         op2 = op2.sig
  32     return op(op1, op2)
  33
  34
  35 class PartitionedSignal:
  36     def __init__(self, mask, *args, **kwargs):
  37         self.sig = Signal(*args, **kwargs)
  38         width = self.sig.shape()[0] # get signal width
  39         self.partpoints = make_partition(mask, width) # create partition points
  40         self.modnames = {}
  41         for name in ['add', 'eq', 'gt', 'ge']:
  42             self.modnames[name] = 0
  43
  44     def set_module(self, m):
  45         self.m = m
  46
  47     def get_modname(self, category):
  48         self.modnames[category] += 1
  49         return "%s%d" % (category, self.modnames[category])
  50
  51     def eq(self, val):
  52         if isinstance(val, PartitionedSignal):
  53             return self.sig.eq(val.sig)
  54         return self.sig.eq(val)
  55
  56     # unary  ops that require partitioning
  57
  58     def __invert__(self):
  59         return Operator("~", [self])
  60     def __neg__(self):
  61         return Operator("-", [self])
  62
  63     # binary ops that don't require partitioning
  64
  65     def __and__(self, other):
  66         return applyop(self, other, and_)
  67
  68     def __rand__(self, other):
  69         return applyop(other, self, and_)
  70
  71     def __or__(self, other):
  72         return applyop(self, other, or_)
  73
  74     def __ror__(self, other):
  75         return applyop(other, self, or_)
  76
  77     def __xor__(self, other):
  78         return applyop(self, other, xor)
  79
  80     def __rxor__(self, other):
  81         return applyop(other, self, xor)
  82
  83     # binary ops that need partitioning
  84
  85     def __add__(self, other):
  86         shape = self.sig.shape()
  87         pa = PartitionedAdder(shape[0], self.partpoints)
  88         setattr(self.m.submodules, self.get_modname('add'), pa)
  89         comb = self.m.d.comb
  90         comb += pa.a.eq(self.sig)
  91         if isinstance(other, PartitionedSignal):
  92             comb += pa.b.eq(other.sig)
  93         else:
  94             comb += pa.b.eq(other)
  95         return pa.output
  96
  97     def __radd__(self, other):
  98         return Operator("+", [other, self])
  99     def __sub__(self, other):
 100         return Operator("-", [self, other])
 101     def __rsub__(self, other):
 102         return Operator("-", [other, self])
 103
 104     def __mul__(self, other):
 105         return Operator("*", [self, other])
 106     def __rmul__(self, other):
 107         return Operator("*", [other, self])
 108
 109     def __check_divisor(self):
 110         width, signed = self.shape()
 111         if signed:
 112             # Python's division semantics and Verilog's division semantics
 113             # differ for negative divisors (Python uses div/mod, Verilog
 114             # uses quo/rem); for now, avoid the issue
 115             # completely by prohibiting such division operations.
 116             raise NotImplementedError(
 117                     "Division by a signed value is not supported")
 118     def __mod__(self, other):
 119         other = Value.cast(other)
 120         other.__check_divisor()
 121         return Operator("%", [self, other])
 122     def __rmod__(self, other):
 123         self.__check_divisor()
 124         return Operator("%", [other, self])
 125     def __floordiv__(self, other):
 126         other = Value.cast(other)
 127         other.__check_divisor()
 128         return Operator("//", [self, other])
 129     def __rfloordiv__(self, other):
 130         self.__check_divisor()
 131         return Operator("//", [other, self])
 132
 133     def __lshift__(self, other):
 134         return Operator("<<", [self, other])
 135     def __rlshift__(self, other):
 136         return Operator("<<", [other, self])
 137     def __rshift__(self, other):
 138         return Operator(">>", [self, other])
 139
 140     # binary comparison ops that need partitioning
 141
 142     def _compare(self, width, op1, op2, opname, optype):
 143         #print (opname, op1, op2)
 144         pa = PartitionedEqGtGe(width, self.partpoints)
 145         setattr(self.m.submodules, self.get_modname(opname), pa)
 146         comb = self.m.d.comb
 147         comb += pa.opcode.eq(optype) # set opcode
 148         if isinstance(op1, PartitionedSignal):
 149             comb += pa.a.eq(op1.sig)
 150         else:
 151             comb += pa.a.eq(op1)
 152         if isinstance(op2, PartitionedSignal):
 153             comb += pa.b.eq(op2.sig)
 154         else:
 155             comb += pa.b.eq(op2)
 156         return pa.output
 157
 158     def __eq__(self, other):
 159         width = self.sig.shape()[0]
 160         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 161
 162     def __ne__(self, other):
 163         width = self.sig.shape()[0]
 164         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 165         ne = Signal(eq.width)
 166         self.m.d.comb += ne.eq(~eq)
 167         return ne
 168
 169     def __gt__(self, other):
 170         width = self.sig.shape()[0]
 171         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 172
 173     def __lt__(self, other):
 174         width = self.sig.shape()[0]
 175         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 176
 177     def __ge__(self, other):
 178         width = self.sig.shape()[0]
 179         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 180
 181     def __le__(self, other):
 182         width = self.sig.shape()[0]
 183         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 184
 185     # useful operators
 186
 187     def bool(self):
 188         """Conversion to boolean.
 189
 190         Returns
 191         -------
 192         Value, out
 193             ``1`` if any bits are set, ``0`` otherwise.
 194         """
 195         return Operator("b", [self])
 196
 197     def any(self):
 198         """Check if any bits are ``1``.
 199
 200         Returns
 201         -------
 202         Value, out
 203             ``1`` if any bits are set, ``0`` otherwise.
 204         """
 205         return Operator("r|", [self])
 206
 207     def all(self):
 208         """Check if all bits are ``1``.
 209
 210         Returns
 211         -------
 212         Value, out
 213             ``1`` if all bits are set, ``0`` otherwise.
 214         """
 215         return Operator("r&", [self])
 216
 217     def xor(self):
 218         """Compute pairwise exclusive-or of every bit.
 219
 220         Returns
 221         -------
 222         Value, out
 223             ``1`` if an odd number of bits are set, ``0`` if an
 224                   even number of bits are set.
 225         """
 226         return Operator("r^", [self])
 227
 228     def implies(premise, conclusion):
 229         """Implication.
 230
 231         Returns
 232         -------
 233         Value, out
 234             ``0`` if ``premise`` is true and ``conclusion`` is not,
 235             ``1`` otherwise.
 236         """
 237         return ~premise | conclusion
 238
 239