src/ieee754/part_mul_add/multiply.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3 """Integer Multiplication."""
   4
   5 from nmigen import Signal, Module, Value, Elaboratable, Cat, C, Mux, Repl
   6 from nmigen.hdl.ast import Assign
   7 from abc import ABCMeta, abstractmethod
   8 from nmigen.cli import main
   9 from functools import reduce
  10 from operator import or_
  11
  12 class PartitionPoints(dict):
  13     """Partition points and corresponding ``Value``s.
  14
  15     The points at where an ALU is partitioned along with ``Value``s that
  16     specify if the corresponding partition points are enabled.
  17
  18     For example: ``{1: True, 5: True, 10: True}`` with
  19     ``width == 16`` specifies that the ALU is split into 4 sections:
  20     * bits 0 <= ``i`` < 1
  21     * bits 1 <= ``i`` < 5
  22     * bits 5 <= ``i`` < 10
  23     * bits 10 <= ``i`` < 16
  24
  25     If the partition_points were instead ``{1: True, 5: a, 10: True}``
  26     where ``a`` is a 1-bit ``Signal``:
  27     * If ``a`` is asserted:
  28         * bits 0 <= ``i`` < 1
  29         * bits 1 <= ``i`` < 5
  30         * bits 5 <= ``i`` < 10
  31         * bits 10 <= ``i`` < 16
  32     * Otherwise
  33         * bits 0 <= ``i`` < 1
  34         * bits 1 <= ``i`` < 10
  35         * bits 10 <= ``i`` < 16
  36     """
  37
  38     def __init__(self, partition_points=None):
  39         """Create a new ``PartitionPoints``.
  40
  41         :param partition_points: the input partition points to values mapping.
  42         """
  43         super().__init__()
  44         if partition_points is not None:
  45             for point, enabled in partition_points.items():
  46                 if not isinstance(point, int):
  47                     raise TypeError("point must be a non-negative integer")
  48                 if point < 0:
  49                     raise ValueError("point must be a non-negative integer")
  50                 self[point] = Value.wrap(enabled)
  51
  52     def like(self, name=None, src_loc_at=0):
  53         """Create a new ``PartitionPoints`` with ``Signal``s for all values.
  54
  55         :param name: the base name for the new ``Signal``s.
  56         """
  57         if name is None:
  58             name = Signal(src_loc_at=1+src_loc_at).name  # get variable name
  59         retval = PartitionPoints()
  60         for point, enabled in self.items():
  61             retval[point] = Signal(enabled.shape(), name=f"{name}_{point}")
  62         return retval
  63
  64     def eq(self, rhs):
  65         """Assign ``PartitionPoints`` using ``Signal.eq``."""
  66         if set(self.keys()) != set(rhs.keys()):
  67             raise ValueError("incompatible point set")
  68         for point, enabled in self.items():
  69             yield enabled.eq(rhs[point])
  70
  71     def as_mask(self, width):
  72         """Create a bit-mask from `self`.
  73
  74         Each bit in the returned mask is clear only if the partition point at
  75         the same bit-index is enabled.
  76
  77         :param width: the bit width of the resulting mask
  78         """
  79         bits = []
  80         for i in range(width):
  81             if i in self:
  82                 bits.append(~self[i])
  83             else:
  84                 bits.append(True)
  85         return Cat(*bits)
  86
  87     def get_max_partition_count(self, width):
  88         """Get the maximum number of partitions.
  89
  90         Gets the number of partitions when all partition points are enabled.
  91         """
  92         retval = 1
  93         for point in self.keys():
  94             if point < width:
  95                 retval += 1
  96         return retval
  97
  98     def fits_in_width(self, width):
  99         """Check if all partition points are smaller than `width`."""
 100         for point in self.keys():
 101             if point >= width:
 102                 return False
 103         return True
 104
 105
 106 class FullAdder(Elaboratable):
 107     """Full Adder.
 108
 109     :attribute in0: the first input
 110     :attribute in1: the second input
 111     :attribute in2: the third input
 112     :attribute sum: the sum output
 113     :attribute carry: the carry output
 114     """
 115
 116     def __init__(self, width):
 117         """Create a ``FullAdder``.
 118
 119         :param width: the bit width of the input and output
 120         """
 121         self.in0 = Signal(width)
 122         self.in1 = Signal(width)
 123         self.in2 = Signal(width)
 124         self.sum = Signal(width)
 125         self.carry = Signal(width)
 126
 127     def elaborate(self, platform):
 128         """Elaborate this module."""
 129         m = Module()
 130         m.d.comb += self.sum.eq(self.in0 ^ self.in1 ^ self.in2)
 131         m.d.comb += self.carry.eq((self.in0 & self.in1)
 132                                   | (self.in1 & self.in2)
 133                                   | (self.in2 & self.in0))
 134         return m
 135
 136
 137 class PartitionedAdder(Elaboratable):
 138     """Partitioned Adder.
 139
 140     :attribute width: the bit width of the input and output. Read-only.
 141     :attribute a: the first input to the adder
 142     :attribute b: the second input to the adder
 143     :attribute output: the sum output
 144     :attribute partition_points: the input partition points. Modification not
 145         supported, except for by ``Signal.eq``.
 146     """
 147
 148     def __init__(self, width, partition_points):
 149         """Create a ``PartitionedAdder``.
 150
 151         :param width: the bit width of the input and output
 152         :param partition_points: the input partition points
 153         """
 154         self.width = width
 155         self.a = Signal(width)
 156         self.b = Signal(width)
 157         self.output = Signal(width)
 158         self.partition_points = PartitionPoints(partition_points)
 159         if not self.partition_points.fits_in_width(width):
 160             raise ValueError("partition_points doesn't fit in width")
 161         expanded_width = 0
 162         for i in range(self.width):
 163             if i in self.partition_points:
 164                 expanded_width += 1
 165             expanded_width += 1
 166         self._expanded_width = expanded_width
 167
 168     def elaborate(self, platform):
 169         """Elaborate this module."""
 170         m = Module()
 171
 172         # intermediates
 173         expanded_a = Signal(self._expanded_width)
 174         expanded_b = Signal(self._expanded_width)
 175         expanded_output = Signal(self._expanded_width)
 176
 177         expanded_index = 0
 178         # store bits in a list, use Cat later.  graphviz is much cleaner
 179         al = []
 180         bl = []
 181         ol = []
 182         ea = []
 183         eb = []
 184         eo = []
 185         # partition points are "breaks" (extra zeros) in what would otherwise
 186         # be a massive long add.
 187         for i in range(self.width):
 188             if i in self.partition_points:
 189                 # add extra bit set to 0 + 0 for enabled partition points
 190                 # and 1 + 0 for disabled partition points
 191                 ea.append(expanded_a[expanded_index])
 192                 al.append(~self.partition_points[i])
 193                 eb.append(expanded_b[expanded_index])
 194                 bl.append(C(0))
 195                 expanded_index += 1
 196             ea.append(expanded_a[expanded_index])
 197             al.append(self.a[i])
 198             eb.append(expanded_b[expanded_index])
 199             bl.append(self.b[i])
 200             eo.append(expanded_output[expanded_index])
 201             ol.append(self.output[i])
 202             expanded_index += 1
 203         # combine above using Cat
 204         m.d.comb += Cat(*ea).eq(Cat(*al))
 205         m.d.comb += Cat(*eb).eq(Cat(*bl))
 206         m.d.comb += Cat(*ol).eq(Cat(*eo))
 207         # use only one addition to take advantage of look-ahead carry and
 208         # special hardware on FPGAs
 209         m.d.comb += expanded_output.eq( expanded_a + expanded_b)
 210         return m
 211
 212
 213 FULL_ADDER_INPUT_COUNT = 3
 214
 215
 216 class AddReduce(Elaboratable):
 217     """Add list of numbers together.
 218
 219     :attribute inputs: input ``Signal``s to be summed. Modification not
 220         supported, except for by ``Signal.eq``.
 221     :attribute register_levels: List of nesting levels that should have
 222         pipeline registers.
 223     :attribute output: output sum.
 224     :attribute partition_points: the input partition points. Modification not
 225         supported, except for by ``Signal.eq``.
 226     """
 227
 228     def __init__(self, inputs, output_width, register_levels, partition_points):
 229         """Create an ``AddReduce``.
 230
 231         :param inputs: input ``Signal``s to be summed.
 232         :param output_width: bit-width of ``output``.
 233         :param register_levels: List of nesting levels that should have
 234             pipeline registers.
 235         :param partition_points: the input partition points.
 236         """
 237         self.inputs = list(inputs)
 238         self._resized_inputs = [
 239             Signal(output_width, name=f"resized_inputs[{i}]")
 240             for i in range(len(self.inputs))]
 241         self.register_levels = list(register_levels)
 242         self.output = Signal(output_width)
 243         self.partition_points = PartitionPoints(partition_points)
 244         if not self.partition_points.fits_in_width(output_width):
 245             raise ValueError("partition_points doesn't fit in output_width")
 246         self._reg_partition_points = self.partition_points.like()
 247         max_level = AddReduce.get_max_level(len(self.inputs))
 248         for level in self.register_levels:
 249             if level > max_level:
 250                 raise ValueError(
 251                     "not enough adder levels for specified register levels")
 252
 253     @staticmethod
 254     def get_max_level(input_count):
 255         """Get the maximum level.
 256
 257         All ``register_levels`` must be less than or equal to the maximum
 258         level.
 259         """
 260         retval = 0
 261         while True:
 262             groups = AddReduce.full_adder_groups(input_count)
 263             if len(groups) == 0:
 264                 return retval
 265             input_count %= FULL_ADDER_INPUT_COUNT
 266             input_count += 2 * len(groups)
 267             retval += 1
 268
 269     def next_register_levels(self):
 270         """``Iterable`` of ``register_levels`` for next recursive level."""
 271         for level in self.register_levels:
 272             if level > 0:
 273                 yield level - 1
 274
 275     @staticmethod
 276     def full_adder_groups(input_count):
 277         """Get ``inputs`` indices for which a full adder should be built."""
 278         return range(0,
 279                      input_count - FULL_ADDER_INPUT_COUNT + 1,
 280                      FULL_ADDER_INPUT_COUNT)
 281
 282     def elaborate(self, platform):
 283         """Elaborate this module."""
 284         m = Module()
 285
 286         # resize inputs to correct bit-width and optionally add in
 287         # pipeline registers
 288         resized_input_assignments = [self._resized_inputs[i].eq(self.inputs[i])
 289                                      for i in range(len(self.inputs))]
 290         if 0 in self.register_levels:
 291             m.d.sync += resized_input_assignments
 292             m.d.sync += self._reg_partition_points.eq(self.partition_points)
 293         else:
 294             m.d.comb += resized_input_assignments
 295             m.d.comb += self._reg_partition_points.eq(self.partition_points)
 296
 297         groups = AddReduce.full_adder_groups(len(self.inputs))
 298         # if there are no full adders to create, then we handle the base cases
 299         # and return, otherwise we go on to the recursive case
 300         if len(groups) == 0:
 301             if len(self.inputs) == 0:
 302                 # use 0 as the default output value
 303                 m.d.comb += self.output.eq(0)
 304             elif len(self.inputs) == 1:
 305                 # handle single input
 306                 m.d.comb += self.output.eq(self._resized_inputs[0])
 307             else:
 308                 # base case for adding 2 or more inputs, which get recursively
 309                 # reduced to 2 inputs
 310                 assert len(self.inputs) == 2
 311                 adder = PartitionedAdder(len(self.output),
 312                                          self._reg_partition_points)
 313                 m.submodules.final_adder = adder
 314                 m.d.comb += adder.a.eq(self._resized_inputs[0])
 315                 m.d.comb += adder.b.eq(self._resized_inputs[1])
 316                 m.d.comb += self.output.eq(adder.output)
 317             return m
 318         # go on to handle recursive case
 319         intermediate_terms = []
 320
 321         def add_intermediate_term(value):
 322             intermediate_term = Signal(
 323                 len(self.output),
 324                 name=f"intermediate_terms[{len(intermediate_terms)}]")
 325             intermediate_terms.append(intermediate_term)
 326             m.d.comb += intermediate_term.eq(value)
 327
 328         # store mask in intermediary (simplifies graph)
 329         part_mask = Signal(len(self.output), reset_less=True)
 330         mask = self._reg_partition_points.as_mask(len(self.output))
 331         m.d.comb += part_mask.eq(mask)
 332
 333         # create full adders for this recursive level.
 334         # this shrinks N terms to 2 * (N // 3) plus the remainder
 335         for i in groups:
 336             adder_i = FullAdder(len(self.output))
 337             setattr(m.submodules, f"adder_{i}", adder_i)
 338             m.d.comb += adder_i.in0.eq(self._resized_inputs[i])
 339             m.d.comb += adder_i.in1.eq(self._resized_inputs[i + 1])
 340             m.d.comb += adder_i.in2.eq(self._resized_inputs[i + 2])
 341             add_intermediate_term(adder_i.sum)
 342             shifted_carry = adder_i.carry << 1
 343             # mask out carry bits to prevent carries between partitions
 344             add_intermediate_term((adder_i.carry << 1) & part_mask)
 345         # handle the remaining inputs.
 346         if len(self.inputs) % FULL_ADDER_INPUT_COUNT == 1:
 347             add_intermediate_term(self._resized_inputs[-1])
 348         elif len(self.inputs) % FULL_ADDER_INPUT_COUNT == 2:
 349             # Just pass the terms to the next layer, since we wouldn't gain
 350             # anything by using a half adder since there would still be 2 terms
 351             # and just passing the terms to the next layer saves gates.
 352             add_intermediate_term(self._resized_inputs[-2])
 353             add_intermediate_term(self._resized_inputs[-1])
 354         else:
 355             assert len(self.inputs) % FULL_ADDER_INPUT_COUNT == 0
 356         # recursive invocation of ``AddReduce``
 357         next_level = AddReduce(intermediate_terms,
 358                                len(self.output),
 359                                self.next_register_levels(),
 360                                self._reg_partition_points)
 361         m.submodules.next_level = next_level
 362         m.d.comb += self.output.eq(next_level.output)
 363         return m
 364
 365
 366 OP_MUL_LOW = 0
 367 OP_MUL_SIGNED_HIGH = 1
 368 OP_MUL_SIGNED_UNSIGNED_HIGH = 2  # a is signed, b is unsigned
 369 OP_MUL_UNSIGNED_HIGH = 3
 370
 371
 372 def get_term(value, shift=0, enabled=None):
 373     if enabled is not None:
 374         value = Mux(enabled, value, 0)
 375     if shift > 0:
 376         value = Cat(Repl(C(0, 1), shift), value)
 377     else:
 378         assert shift == 0
 379     return value
 380
 381
 382 class ProductTerm(Elaboratable):
 383
 384     def __init__(self, width, twidth, pbwid, a_index, b_index):
 385         self.a_index = a_index
 386         self.b_index = b_index
 387         shift = 8 * (self.a_index + self.b_index)
 388         self.pwidth = width
 389         self.twidth = twidth
 390         self.width = width*2
 391         self.shift = shift
 392
 393         self.ti = Signal(self.width, reset_less=True)
 394         self.term = Signal(twidth, reset_less=True)
 395         self.a = Signal(twidth//2, reset_less=True)
 396         self.b = Signal(twidth//2, reset_less=True)
 397         self.pb_en = Signal(pbwid, reset_less=True)
 398
 399         self.tl = tl = []
 400         min_index = min(self.a_index, self.b_index)
 401         max_index = max(self.a_index, self.b_index)
 402         for i in range(min_index, max_index):
 403             tl.append(self.pb_en[i])
 404         name = "te_%d_%d" % (self.a_index, self.b_index)
 405         if len(tl) > 0:
 406             term_enabled = Signal(name=name, reset_less=True)
 407         else:
 408             term_enabled = None
 409         self.enabled = term_enabled
 410         self.term.name = "term_%d_%d" % (a_index, b_index) # rename
 411
 412     def elaborate(self, platform):
 413
 414         m = Module()
 415         if self.enabled is not None:
 416             m.d.comb += self.enabled.eq(~(Cat(*self.tl).bool()))
 417
 418         bsa = Signal(self.width, reset_less=True)
 419         bsb = Signal(self.width, reset_less=True)
 420         a_index, b_index = self.a_index, self.b_index
 421         pwidth = self.pwidth
 422         m.d.comb += bsa.eq(self.a.bit_select(a_index * pwidth, pwidth))
 423         m.d.comb += bsb.eq(self.b.bit_select(b_index * pwidth, pwidth))
 424         m.d.comb += self.ti.eq(bsa * bsb)
 425         m.d.comb += self.term.eq(get_term(self.ti, self.shift, self.enabled))
 426         """
 427         #TODO: sort out width issues, get inputs a/b switched on/off.
 428         #data going into Muxes is 1/2 the required width
 429
 430         pwidth = self.pwidth
 431         width = self.width
 432         bsa = Signal(self.twidth//2, reset_less=True)
 433         bsb = Signal(self.twidth//2, reset_less=True)
 434         asel = Signal(width, reset_less=True)
 435         bsel = Signal(width, reset_less=True)
 436         a_index, b_index = self.a_index, self.b_index
 437         m.d.comb += asel.eq(self.a.bit_select(a_index * pwidth, pwidth))
 438         m.d.comb += bsel.eq(self.b.bit_select(b_index * pwidth, pwidth))
 439         m.d.comb += bsa.eq(get_term(asel, self.shift, self.enabled))
 440         m.d.comb += bsb.eq(get_term(bsel, self.shift, self.enabled))
 441         m.d.comb += self.ti.eq(bsa * bsb)
 442         m.d.comb += self.term.eq(self.ti)
 443         """
 444
 445         return m
 446
 447
 448 class ProductTerms(Elaboratable):
 449
 450     def __init__(self, width, twidth, pbwid, a_index, blen):
 451         self.a_index = a_index
 452         self.blen = blen
 453         self.pwidth = width
 454         self.twidth = twidth
 455         self.pbwid = pbwid
 456         self.a = Signal(twidth//2, reset_less=True)
 457         self.b = Signal(twidth//2, reset_less=True)
 458         self.pb_en = Signal(pbwid, reset_less=True)
 459         self.terms = [Signal(twidth, name="term%d"%i, reset_less=True) \
 460                             for i in range(blen)]
 461
 462     def elaborate(self, platform):
 463
 464         m = Module()
 465
 466         for b_index in range(self.blen):
 467             t = ProductTerm(self.pwidth, self.twidth, self.pbwid,
 468                             self.a_index, b_index)
 469             setattr(m.submodules, "term_%d" % b_index, t)
 470
 471             m.d.comb += t.a.eq(self.a)
 472             m.d.comb += t.b.eq(self.b)
 473             m.d.comb += t.pb_en.eq(self.pb_en)
 474
 475             m.d.comb += self.terms[b_index].eq(t.term)
 476
 477         return m
 478
 479
 480 class Part(Elaboratable):
 481     def __init__(self, width, n_parts, n_levels, pbwid):
 482
 483         # inputs
 484         self.a = Signal(64)
 485         self.b = Signal(64)
 486         self.a_signed = [Signal(name=f"a_signed_{i}") for i in range(8)]
 487         self.b_signed = [Signal(name=f"_b_signed_{i}") for i in range(8)]
 488         self.pbs = Signal(pbwid, reset_less=True)
 489
 490         # outputs
 491         self.parts = [Signal(name=f"part_{i}") for i in range(n_parts)]
 492         self.delayed_parts = [
 493             [Signal(name=f"delayed_part_{delay}_{i}")
 494              for i in range(n_parts)]
 495                 for delay in range(n_levels)]
 496         # XXX REALLY WEIRD BUG - have to take a copy of the last delayed_parts
 497         self.dplast = [Signal(name=f"dplast_{i}")
 498                          for i in range(n_parts)]
 499
 500         self.not_a_term = Signal(width)
 501         self.neg_lsb_a_term = Signal(width)
 502         self.not_b_term = Signal(width)
 503         self.neg_lsb_b_term = Signal(width)
 504
 505     def elaborate(self, platform):
 506         m = Module()
 507
 508         pbs, parts, delayed_parts = self.pbs, self.parts, self.delayed_parts
 509         byte_count = 8 // len(parts)
 510         for i in range(len(parts)):
 511             pbl = []
 512             pbl.append(~pbs[i * byte_count - 1])
 513             for j in range(i * byte_count, (i + 1) * byte_count - 1):
 514                 pbl.append(pbs[j])
 515             pbl.append(~pbs[(i + 1) * byte_count - 1])
 516             value = Signal(len(pbl), reset_less=True)
 517             m.d.comb += value.eq(Cat(*pbl))
 518             m.d.comb += parts[i].eq(~(value).bool())
 519             m.d.comb += delayed_parts[0][i].eq(parts[i])
 520             m.d.sync += [delayed_parts[j + 1][i].eq(delayed_parts[j][i])
 521                          for j in range(len(delayed_parts)-1)]
 522             m.d.comb += self.dplast[i].eq(delayed_parts[-1][i])
 523
 524         not_a_term, neg_lsb_a_term, not_b_term, neg_lsb_b_term = \
 525                 self.not_a_term, self.neg_lsb_a_term, \
 526                 self.not_b_term, self.neg_lsb_b_term
 527
 528         byte_width = 8 // len(parts)
 529         bit_width = 8 * byte_width
 530         nat, nbt, nla, nlb = [], [], [], []
 531         for i in range(len(parts)):
 532             be = parts[i] & self.a[(i + 1) * bit_width - 1] \
 533                 & self.a_signed[i * byte_width]
 534             ae = parts[i] & self.b[(i + 1) * bit_width - 1] \
 535                 & self.b_signed[i * byte_width]
 536             a_enabled = Signal(name="a_en_%d" % i, reset_less=True)
 537             b_enabled = Signal(name="b_en_%d" % i, reset_less=True)
 538             m.d.comb += a_enabled.eq(ae)
 539             m.d.comb += b_enabled.eq(be)
 540
 541             # for 8-bit values: form a * 0xFF00 by using -a * 0x100, the
 542             # negation operation is split into a bitwise not and a +1.
 543             # likewise for 16, 32, and 64-bit values.
 544             nat.append(Mux(a_enabled,
 545                     Cat(Repl(0, bit_width),
 546                         ~self.a.bit_select(bit_width * i, bit_width)),
 547                     0))
 548
 549             nla.append(Cat(Repl(0, bit_width), a_enabled,
 550                            Repl(0, bit_width-1)))
 551
 552             nbt.append(Mux(b_enabled,
 553                     Cat(Repl(0, bit_width),
 554                         ~self.b.bit_select(bit_width * i, bit_width)),
 555                     0))
 556
 557             nlb.append(Cat(Repl(0, bit_width), b_enabled,
 558                            Repl(0, bit_width-1)))
 559
 560         m.d.comb += [not_a_term.eq(Cat(*nat)),
 561                      not_b_term.eq(Cat(*nbt)),
 562                      neg_lsb_a_term.eq(Cat(*nla)),
 563                      neg_lsb_b_term.eq(Cat(*nlb)),
 564                     ]
 565
 566         return m
 567
 568
 569 class IntermediateOut(Elaboratable):
 570     def __init__(self, width, out_wid, n_parts):
 571         self.width = width
 572         self.n_parts = n_parts
 573         self.delayed_part_ops = [Signal(2, name="dpop%d" % i, reset_less=True)
 574                                      for i in range(8)]
 575         self.intermed = Signal(out_wid, reset_less=True)
 576         self.output = Signal(out_wid//2, reset_less=True)
 577
 578     def elaborate(self, platform):
 579         m = Module()
 580
 581         ol = []
 582         w = self.width
 583         sel = w // 8
 584         for i in range(self.n_parts):
 585             op = Signal(w, reset_less=True, name="op%d_%d" % (w, i))
 586             m.d.comb += op.eq(
 587                 Mux(self.delayed_part_ops[sel * i] == OP_MUL_LOW,
 588                     self.intermed.bit_select(i * w*2, w),
 589                     self.intermed.bit_select(i * w*2 + w, w)))
 590             ol.append(op)
 591         m.d.comb += self.output.eq(Cat(*ol))
 592
 593         return m
 594
 595
 596 class FinalOut(Elaboratable):
 597     def __init__(self, out_wid):
 598         # inputs
 599         self.d8 = [Signal(name=f"d8_{i}", reset_less=True) for i in range(8)]
 600         self.d16 = [Signal(name=f"d16_{i}", reset_less=True) for i in range(4)]
 601         self.d32 = [Signal(name=f"d32_{i}", reset_less=True) for i in range(2)]
 602
 603         self.i8 = Signal(out_wid, reset_less=True)
 604         self.i16 = Signal(out_wid, reset_less=True)
 605         self.i32 = Signal(out_wid, reset_less=True)
 606         self.i64 = Signal(out_wid, reset_less=True)
 607
 608         # output
 609         self.out = Signal(out_wid, reset_less=True)
 610
 611     def elaborate(self, platform):
 612         m = Module()
 613         ol = []
 614         for i in range(8):
 615             op = Signal(8, reset_less=True, name="op_%d" % i)
 616             m.d.comb += op.eq(
 617                 Mux(self.d8[i] | self.d16[i // 2],
 618                     Mux(self.d8[i], self.i8.bit_select(i * 8, 8),
 619                                      self.i16.bit_select(i * 8, 8)),
 620                     Mux(self.d32[i // 4], self.i32.bit_select(i * 8, 8),
 621                                           self.i64.bit_select(i * 8, 8))))
 622             ol.append(op)
 623         m.d.comb += self.out.eq(Cat(*ol))
 624         return m
 625
 626
 627 class OrMod(Elaboratable):
 628     def __init__(self, wid):
 629         self.wid = wid
 630         self.orin = [Signal(wid, name="orin%d" % i, reset_less=True)
 631                      for i in range(4)]
 632         self.orout = Signal(wid, reset_less=True)
 633
 634     def elaborate(self, platform):
 635         m = Module()
 636         or1 = Signal(self.wid, reset_less=True)
 637         or2 = Signal(self.wid, reset_less=True)
 638         m.d.comb += or1.eq(self.orin[0] | self.orin[1])
 639         m.d.comb += or2.eq(self.orin[2] | self.orin[3])
 640         m.d.comb += self.orout.eq(or1 | or2)
 641
 642         return m
 643
 644
 645 class Signs(Elaboratable):
 646
 647     def __init__(self):
 648         self.part_ops = Signal(2, reset_less=True)
 649         self.a_signed = Signal(reset_less=True)
 650         self.b_signed = Signal(reset_less=True)
 651
 652     def elaborate(self, platform):
 653
 654         m = Module()
 655
 656         asig = self.part_ops != OP_MUL_UNSIGNED_HIGH
 657         bsig = (self.part_ops == OP_MUL_LOW) \
 658                     | (self.part_ops == OP_MUL_SIGNED_HIGH)
 659         m.d.comb += self.a_signed.eq(asig)
 660         m.d.comb += self.b_signed.eq(bsig)
 661
 662         return m
 663
 664
 665 class Mul8_16_32_64(Elaboratable):
 666     """Signed/Unsigned 8/16/32/64-bit partitioned integer multiplier.
 667
 668     Supports partitioning into any combination of 8, 16, 32, and 64-bit
 669     partitions on naturally-aligned boundaries. Supports the operation being
 670     set for each partition independently.
 671
 672     :attribute part_pts: the input partition points. Has a partition point at
 673         multiples of 8 in 0 < i < 64. Each partition point's associated
 674         ``Value`` is a ``Signal``. Modification not supported, except for by
 675         ``Signal.eq``.
 676     :attribute part_ops: the operation for each byte. The operation for a
 677         particular partition is selected by assigning the selected operation
 678         code to each byte in the partition. The allowed operation codes are:
 679
 680         :attribute OP_MUL_LOW: the LSB half of the product. Equivalent to
 681             RISC-V's `mul` instruction.
 682         :attribute OP_MUL_SIGNED_HIGH: the MSB half of the product where both
 683             ``a`` and ``b`` are signed. Equivalent to RISC-V's `mulh`
 684             instruction.
 685         :attribute OP_MUL_SIGNED_UNSIGNED_HIGH: the MSB half of the product
 686             where ``a`` is signed and ``b`` is unsigned. Equivalent to RISC-V's
 687             `mulhsu` instruction.
 688         :attribute OP_MUL_UNSIGNED_HIGH: the MSB half of the product where both
 689             ``a`` and ``b`` are unsigned. Equivalent to RISC-V's `mulhu`
 690             instruction.
 691     """
 692
 693     def __init__(self, register_levels= ()):
 694
 695         # parameter(s)
 696         self.register_levels = list(register_levels)
 697
 698         # inputs
 699         self.part_pts = PartitionPoints()
 700         for i in range(8, 64, 8):
 701             self.part_pts[i] = Signal(name=f"part_pts_{i}")
 702         self.part_ops = [Signal(2, name=f"part_ops_{i}") for i in range(8)]
 703         self.a = Signal(64)
 704         self.b = Signal(64)
 705
 706         # intermediates (needed for unit tests)
 707         self._intermediate_output = Signal(128)
 708
 709         # output
 710         self.output = Signal(64)
 711
 712     def _part_byte(self, index):
 713         if index == -1 or index == 7:
 714             return C(True, 1)
 715         assert index >= 0 and index < 8
 716         return self.part_pts[index * 8 + 8]
 717
 718     def elaborate(self, platform):
 719         m = Module()
 720
 721         # collect part-bytes
 722         pbs = Signal(8, reset_less=True)
 723         tl = []
 724         for i in range(8):
 725             pb = Signal(name="pb%d" % i, reset_less=True)
 726             m.d.comb += pb.eq(self._part_byte(i))
 727             tl.append(pb)
 728         m.d.comb += pbs.eq(Cat(*tl))
 729
 730         # local variables
 731         signs = []
 732         for i in range(8):
 733             s = Signs()
 734             signs.append(s)
 735             setattr(m.submodules, "signs%d" % i, s)
 736             m.d.comb += s.part_ops.eq(self.part_ops[i])
 737
 738         delayed_part_ops = [
 739             [Signal(2, name=f"_delayed_part_ops_{delay}_{i}")
 740              for i in range(8)]
 741             for delay in range(1 + len(self.register_levels))]
 742         for i in range(len(self.part_ops)):
 743             m.d.comb += delayed_part_ops[0][i].eq(self.part_ops[i])
 744             m.d.sync += [delayed_part_ops[j + 1][i].eq(delayed_part_ops[j][i])
 745                          for j in range(len(self.register_levels))]
 746
 747         n_levels = len(self.register_levels)+1
 748         m.submodules.part_8 = part_8 = Part(128, 8, n_levels, 8)
 749         m.submodules.part_16 = part_16 = Part(128, 4, n_levels, 8)
 750         m.submodules.part_32 = part_32 = Part(128, 2, n_levels, 8)
 751         m.submodules.part_64 = part_64 = Part(128, 1, n_levels, 8)
 752         nat_l, nbt_l, nla_l, nlb_l = [], [], [], []
 753         for mod in [part_8, part_16, part_32, part_64]:
 754             m.d.comb += mod.a.eq(self.a)
 755             m.d.comb += mod.b.eq(self.b)
 756             for i in range(len(signs)):
 757                 m.d.comb += mod.a_signed[i].eq(signs[i].a_signed)
 758                 m.d.comb += mod.b_signed[i].eq(signs[i].b_signed)
 759             m.d.comb += mod.pbs.eq(pbs)
 760             nat_l.append(mod.not_a_term)
 761             nbt_l.append(mod.not_b_term)
 762             nla_l.append(mod.neg_lsb_a_term)
 763             nlb_l.append(mod.neg_lsb_b_term)
 764
 765         terms = []
 766
 767         for a_index in range(8):
 768             t = ProductTerms(8, 128, 8, a_index, 8)
 769             setattr(m.submodules, "terms_%d" % a_index, t)
 770
 771             m.d.comb += t.a.eq(self.a)
 772             m.d.comb += t.b.eq(self.b)
 773             m.d.comb += t.pb_en.eq(pbs)
 774
 775             for term in t.terms:
 776                 terms.append(term)
 777
 778         # it's fine to bitwise-or data together since they are never enabled
 779         # at the same time
 780         m.submodules.nat_or = nat_or = OrMod(128)
 781         m.submodules.nbt_or = nbt_or = OrMod(128)
 782         m.submodules.nla_or = nla_or = OrMod(128)
 783         m.submodules.nlb_or = nlb_or = OrMod(128)
 784         for l, mod in [(nat_l, nat_or),
 785                              (nbt_l, nbt_or),
 786                              (nla_l, nla_or),
 787                              (nlb_l, nlb_or)]:
 788             for i in range(len(l)):
 789                 m.d.comb += mod.orin[i].eq(l[i])
 790             terms.append(mod.orout)
 791
 792         expanded_part_pts = PartitionPoints()
 793         for i, v in self.part_pts.items():
 794             signal = Signal(name=f"expanded_part_pts_{i*2}", reset_less=True)
 795             expanded_part_pts[i * 2] = signal
 796             m.d.comb += signal.eq(v)
 797
 798         add_reduce = AddReduce(terms,
 799                                128,
 800                                self.register_levels,
 801                                expanded_part_pts)
 802         m.submodules.add_reduce = add_reduce
 803         m.d.comb += self._intermediate_output.eq(add_reduce.output)
 804         # create _output_64
 805         m.submodules.io64 = io64 = IntermediateOut(64, 128, 1)
 806         m.d.comb += io64.intermed.eq(self._intermediate_output)
 807         for i in range(8):
 808             m.d.comb += io64.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
 809
 810         # create _output_32
 811         m.submodules.io32 = io32 = IntermediateOut(32, 128, 2)
 812         m.d.comb += io32.intermed.eq(self._intermediate_output)
 813         for i in range(8):
 814             m.d.comb += io32.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
 815
 816         # create _output_16
 817         m.submodules.io16 = io16 = IntermediateOut(16, 128, 4)
 818         m.d.comb += io16.intermed.eq(self._intermediate_output)
 819         for i in range(8):
 820             m.d.comb += io16.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
 821
 822         # create _output_8
 823         m.submodules.io8 = io8 = IntermediateOut(8, 128, 8)
 824         m.d.comb += io8.intermed.eq(self._intermediate_output)
 825         for i in range(8):
 826             m.d.comb += io8.delayed_part_ops[i].eq(delayed_part_ops[-1][i])
 827
 828         # final output
 829         m.submodules.fo = fo = FinalOut(64)
 830         for i in range(len(part_8.delayed_parts[-1])):
 831             m.d.comb += fo.d8[i].eq(part_8.dplast[i])
 832         for i in range(len(part_16.delayed_parts[-1])):
 833             m.d.comb += fo.d16[i].eq(part_16.dplast[i])
 834         for i in range(len(part_32.delayed_parts[-1])):
 835             m.d.comb += fo.d32[i].eq(part_32.dplast[i])
 836         m.d.comb += fo.i8.eq(io8.output)
 837         m.d.comb += fo.i16.eq(io16.output)
 838         m.d.comb += fo.i32.eq(io32.output)
 839         m.d.comb += fo.i64.eq(io64.output)
 840         m.d.comb += self.output.eq(fo.out)
 841
 842         return m
 843
 844
 845 if __name__ == "__main__":
 846     m = Mul8_16_32_64()
 847     main(m, ports=[m.a,
 848                    m.b,
 849                    m._intermediate_output,
 850                    m.output,
 851                    *m.part_ops,
 852                    *m.part_pts.values()])