Reverse order of operations in implies()

[ieee754fpu.git] / src / ieee754 / part / partsig.py

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 53561d4bcc97c0dca31981261428b48d2e69dfff..ab14bf9909fff362e132fab4b676bb228d9fd121 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -18,6 +18,7 @@ nmigen.Case, or other constructs: only Mux and other logic.
 
 from ieee754.part_mul_add.adder import PartitionedAdder
 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
+from ieee754.part_bits.xor import PartitionedXOR
 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
 from ieee754.part_mul_add.partpoints import make_partition, PartitionPoints
@@ -46,7 +47,7 @@ class PartitionedSignal:
         else:
             self.partpoints = make_partition(mask, width)
         self.modnames = {}
-        for name in ['add', 'eq', 'gt', 'ge', 'ls']:
+        for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor']:
             self.modnames[name] = 0
 
     def set_module(self, m):
@@ -67,8 +68,8 @@ class PartitionedSignal:
     # unary ops that require partitioning
 
     def __neg__(self):
-        z = Const(0, len(self.partpoints)+1)
-        result, _ = self.add_op(self, ~0, carry=z)  # TODO, subop
+        z = Const(0, len(self.sig))
+        result, _ = self.sub_op(z, self)
         return result
 
     # binary ops that don't require partitioning
@@ -281,6 +282,7 @@ class PartitionedSignal:
         Value, out
             ``1`` if any bits are set, ``0`` otherwise.
         """
+        return self != Const(0) # leverage the __ne__ operator here
         return Operator("r|", [self])
 
     def all(self):
@@ -302,9 +304,11 @@ class PartitionedSignal:
             ``1`` if an odd number of bits are set, ``0`` if an
                   even number of bits are set.
         """
-        # XXXX TODO: return partition-mask-sized set of bits
-        raise NotImplementedError
-        return Operator("r^", [self])
+        width = len(self.sig)
+        pa = PartitionedXOR(width, self.partpoints)
+        setattr(self.m.submodules, self.get_modname("xor"), pa)
+        self.m.d.comb += pa.a.eq(self.sig)
+        return pa.output
 
     def implies(premise, conclusion):
         """Implication.
@@ -316,4 +320,4 @@ class PartitionedSignal:
             ``1`` otherwise.
         """
         # amazingly, this should actually work.
-        return ~premise | conclusion
+        return conclusion | ~premise