+ nir_ssa_def *offset = nir_iadd_imm(b, nir_ssa_for_src(b, intrin->src[0], 1),
+ nir_intrinsic_base(intrin));
+
+ nir_ssa_def *data;
+ if (state->pdevice->use_softpin) {
+ unsigned load_size = intrin->dest.ssa.num_components *
+ intrin->dest.ssa.bit_size / 8;
+ unsigned load_align = intrin->dest.ssa.bit_size / 8;
+
+ assert(load_size < b->shader->constant_data_size);
+ unsigned max_offset = b->shader->constant_data_size - load_size;
+ offset = nir_umin(b, offset, nir_imm_int(b, max_offset));
+
+ nir_ssa_def *const_data_base_addr = nir_pack_64_2x32_split(b,
+ nir_load_reloc_const_intel(b, ANV_SHADER_RELOC_CONST_DATA_ADDR_LOW),
+ nir_load_reloc_const_intel(b, ANV_SHADER_RELOC_CONST_DATA_ADDR_HIGH));
+
+ data = nir_load_global(b, nir_iadd(b, const_data_base_addr,
+ nir_u2u64(b, offset)),
+ load_align,
+ intrin->dest.ssa.num_components,
+ intrin->dest.ssa.bit_size);
+ } else {
+ nir_ssa_def *index = nir_imm_int(b, state->constants_offset);
+
+ nir_intrinsic_instr *load_ubo =
+ nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
+ load_ubo->num_components = intrin->num_components;
+ load_ubo->src[0] = nir_src_for_ssa(index);
+ load_ubo->src[1] = nir_src_for_ssa(offset);
+ nir_intrinsic_set_align(load_ubo, intrin->dest.ssa.bit_size / 8, 0);
+ nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
+ intrin->dest.ssa.num_components,
+ intrin->dest.ssa.bit_size, NULL);
+ nir_builder_instr_insert(b, &load_ubo->instr);
+ data = &load_ubo->dest.ssa;
+ }