src/openpower/decoder/isa/test_caller_svindex.py

   1 """SVP64 unit test for svindex
   2 svindex SVG,rmm,SVd,ew,yx,mr,sk
   3 """
   4 from nmigen import Module, Signal
   5 from nmigen.back.pysim import Simulator, Delay, Settle
   6 from nmutil.formaltest import FHDLTestCase
   7 import unittest
   8 from openpower.decoder.isa.caller import ISACaller
   9 from openpower.decoder.power_decoder import (create_pdecode)
  10 from openpower.decoder.power_decoder2 import (PowerDecode2)
  11 from openpower.simulator.program import Program
  12 from openpower.decoder.isa.caller import ISACaller, SVP64State, CRFields
  13 from openpower.decoder.selectable_int import SelectableInt
  14 from openpower.decoder.orderedset import OrderedSet
  15 from openpower.decoder.isa.all import ISA
  16 from openpower.decoder.isa.test_caller import Register, run_tst
  17 from openpower.sv.trans.svp64 import SVP64Asm
  18 from openpower.consts import SVP64CROffs
  19 from copy import deepcopy
  20
  21
  22 class SVSTATETestCase(FHDLTestCase):
  23
  24     def _check_regs(self, sim, expected):
  25         print ("GPR")
  26         sim.gpr.dump()
  27         for i in range(32):
  28             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64),
  29             "GPR %d %x expected %x" % (i, sim.gpr(i).value, expected[i]))
  30
  31     def test_0_sv_index(self):
  32         """sets VL=10 (via SVSTATE) then does svindex, checks SPRs after
  33         """
  34         isa = SVP64Asm(['svindex 1, 15, 5, 0, 0, 0, 0'
  35                        ])
  36         lst = list(isa)
  37         print ("listing", lst)
  38
  39         # initial values in GPR regfile
  40         initial_regs = [0] * 32
  41         initial_regs[9] = 0x1234
  42         initial_regs[10] = 0x1111
  43         initial_regs[5] = 0x4321
  44         initial_regs[6] = 0x2223
  45
  46         # SVSTATE vl=10
  47         svstate = SVP64State()
  48         svstate.vl = 10 # VL
  49         svstate.maxvl = 10 # MAXVL
  50         print ("SVSTATE", bin(svstate.asint()))
  51
  52         # copy before running
  53         expected_regs = deepcopy(initial_regs)
  54         #expected_regs[1] = 0x3334
  55
  56         with Program(lst, bigendian=False) as program:
  57             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
  58             self._check_regs(sim, expected_regs)
  59
  60             print (sim.spr)
  61             SVSHAPE0 = sim.spr['SVSHAPE0']
  62             print ("SVSTATE after", bin(sim.svstate.asint()))
  63             print ("        vl", bin(sim.svstate.vl))
  64             print ("        mvl", bin(sim.svstate.maxvl))
  65             print ("    srcstep", bin(sim.svstate.srcstep))
  66             print ("    dststep", bin(sim.svstate.dststep))
  67             print ("      RMpst", bin(sim.svstate.RMpst))
  68             print ("       SVme", bin(sim.svstate.SVme))
  69             print ("        mo0", bin(sim.svstate.mo0))
  70             print ("        mo1", bin(sim.svstate.mo1))
  71             print ("        mi0", bin(sim.svstate.mi0))
  72             print ("        mi1", bin(sim.svstate.mi1))
  73             print ("        mi2", bin(sim.svstate.mi2))
  74             print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
  75             print ("STATE0 xdim", SVSHAPE0.xdimsz)
  76             print ("STATE0 ydim", SVSHAPE0.ydimsz)
  77             print ("STATE0 skip", bin(SVSHAPE0.skip))
  78             print ("STATE0  inv", SVSHAPE0.invxyz)
  79             print ("STATE0order", SVSHAPE0.order)
  80             self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
  81             self.assertEqual(sim.svstate.SVme, 0b01111) # same as rmm
  82             # rmm is 0b01111 which means mi0=0 mi1=1 mi2=2 mo0=3 mo1=0
  83             self.assertEqual(sim.svstate.mi0, 0)
  84             self.assertEqual(sim.svstate.mi1, 1)
  85             self.assertEqual(sim.svstate.mi2, 2)
  86             self.assertEqual(sim.svstate.mo0, 3)
  87             self.assertEqual(sim.svstate.mo1, 0)
  88             for i in range(4):
  89                 shape = sim.spr['SVSHAPE%d' % i]
  90                 self.assertEqual(shape.svgpr, 2) # SVG is shifted up by 1
  91
  92     def test_0_sv_index_add(self):
  93         """sets VL=6 (via SVSTATE) then does svindex, and an add.
  94
  95         only RA is re-mapped via Indexing, not RB or RT
  96         """
  97         isa = SVP64Asm(['svindex 8, 1, 1, 0, 0, 0, 0',
  98                         'sv.add *8, *0, *0',
  99                        ])
 100         lst = list(isa)
 101         print ("listing", lst)
 102
 103         # initial values in GPR regfile
 104         initial_regs = [0] * 32
 105         idxs = [1, 0, 5, 2, 4, 3] # random enough
 106         for i in range(6):
 107             initial_regs[16+i] = idxs[i]
 108             initial_regs[i] = i
 109
 110         # SVSTATE vl=10
 111         svstate = SVP64State()
 112         svstate.vl = 6 # VL
 113         svstate.maxvl = 6 # MAXVL
 114         print ("SVSTATE", bin(svstate.asint()))
 115
 116         # copy before running
 117         expected_regs = deepcopy(initial_regs)
 118         for i in range(6):
 119             RA = initial_regs[0+idxs[i]]
 120             RB = initial_regs[0+i]
 121             expected_regs[i+8] = RA+RB
 122             print ("expected", i, expected_regs[i+8])
 123
 124         with Program(lst, bigendian=False) as program:
 125             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 126
 127             print (sim.spr)
 128             SVSHAPE0 = sim.spr['SVSHAPE0']
 129             print ("SVSTATE after", bin(sim.svstate.asint()))
 130             print ("        vl", bin(sim.svstate.vl))
 131             print ("        mvl", bin(sim.svstate.maxvl))
 132             print ("    srcstep", bin(sim.svstate.srcstep))
 133             print ("    dststep", bin(sim.svstate.dststep))
 134             print ("      RMpst", bin(sim.svstate.RMpst))
 135             print ("       SVme", bin(sim.svstate.SVme))
 136             print ("        mo0", bin(sim.svstate.mo0))
 137             print ("        mo1", bin(sim.svstate.mo1))
 138             print ("        mi0", bin(sim.svstate.mi0))
 139             print ("        mi1", bin(sim.svstate.mi1))
 140             print ("        mi2", bin(sim.svstate.mi2))
 141             print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
 142             print (sim.gpr.dump())
 143             self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
 144             self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
 145             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 146             self.assertEqual(sim.svstate.mi0, 0)
 147             self.assertEqual(sim.svstate.mi1, 0)
 148             self.assertEqual(sim.svstate.mi2, 0)
 149             self.assertEqual(sim.svstate.mo0, 0)
 150             self.assertEqual(sim.svstate.mo1, 0)
 151             self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
 152             for i in range(1,4):
 153                 shape = sim.spr['SVSHAPE%d' % i]
 154                 self.assertEqual(shape.svgpr, 0)
 155             self._check_regs(sim, expected_regs)
 156
 157     def test_1_sv_index_add(self):
 158         """sets VL=6 (via SVSTATE) then does modulo 3 svindex, and an add.
 159
 160         only RA is re-mapped via Indexing, not RB or RT
 161         """
 162         isa = SVP64Asm(['svindex 8, 1, 3, 0, 0, 0, 0',
 163                         'sv.add *8, *0, *0',
 164                        ])
 165         lst = list(isa)
 166         print ("listing", lst)
 167
 168         # initial values in GPR regfile
 169         initial_regs = [0] * 32
 170         idxs = [1, 0, 5, 2, 4, 3] # random enough
 171         for i in range(6):
 172             initial_regs[16+i] = idxs[i]
 173             initial_regs[i] = i
 174
 175         # SVSTATE vl=10
 176         svstate = SVP64State()
 177         svstate.vl = 6 # VL
 178         svstate.maxvl = 6 # MAXVL
 179         print ("SVSTATE", bin(svstate.asint()))
 180
 181         # copy before running
 182         expected_regs = deepcopy(initial_regs)
 183         for i in range(6):
 184             RA = initial_regs[0+idxs[i%3]] # modulo 3 but still indexed
 185             RB = initial_regs[0+i]
 186             expected_regs[i+8] = RA+RB
 187             print ("expected", i, expected_regs[i+8])
 188
 189         with Program(lst, bigendian=False) as program:
 190             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 191
 192             print (sim.spr)
 193             SVSHAPE0 = sim.spr['SVSHAPE0']
 194             print ("SVSTATE after", bin(sim.svstate.asint()))
 195             print ("        vl", bin(sim.svstate.vl))
 196             print ("        mvl", bin(sim.svstate.maxvl))
 197             print ("    srcstep", bin(sim.svstate.srcstep))
 198             print ("    dststep", bin(sim.svstate.dststep))
 199             print ("      RMpst", bin(sim.svstate.RMpst))
 200             print ("       SVme", bin(sim.svstate.SVme))
 201             print ("        mo0", bin(sim.svstate.mo0))
 202             print ("        mo1", bin(sim.svstate.mo1))
 203             print ("        mi0", bin(sim.svstate.mi0))
 204             print ("        mi1", bin(sim.svstate.mi1))
 205             print ("        mi2", bin(sim.svstate.mi2))
 206             print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
 207             print ("STATE0 xdim", SVSHAPE0.xdimsz)
 208             print ("STATE0 ydim", SVSHAPE0.ydimsz)
 209             print ("STATE0 skip", bin(SVSHAPE0.skip))
 210             print ("STATE0  inv", SVSHAPE0.invxyz)
 211             print ("STATE0order", SVSHAPE0.order)
 212             print (sim.gpr.dump())
 213             self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
 214             self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
 215             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 216             self.assertEqual(sim.svstate.mi0, 0)
 217             self.assertEqual(sim.svstate.mi1, 0)
 218             self.assertEqual(sim.svstate.mi2, 0)
 219             self.assertEqual(sim.svstate.mo0, 0)
 220             self.assertEqual(sim.svstate.mo1, 0)
 221             self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
 222             for i in range(1,4):
 223                 shape = sim.spr['SVSHAPE%d' % i]
 224                 self.assertEqual(shape.svgpr, 0)
 225             self._check_regs(sim, expected_regs)
 226
 227     def test_2_sv_index_add(self):
 228         """sets VL=6 (via SVSTATE) then does 2D remapped svindex, and an add.
 229
 230         dim=3,yx=1
 231         only RA is re-mapped via Indexing, not RB or RT
 232         """
 233         isa = SVP64Asm(['svindex 8, 1, 3, 0, 1, 0, 0',
 234                         'sv.add *8, *0, *0',
 235                        ])
 236         lst = list(isa)
 237         print ("listing", lst)
 238
 239         # initial values in GPR regfile
 240         initial_regs = [0] * 32
 241         idxs = [1, 0, 5, 2, 4, 3] # random enough
 242         for i in range(6):
 243             initial_regs[16+i] = idxs[i]
 244             initial_regs[i] = i
 245
 246         # SVSTATE vl=10
 247         svstate = SVP64State()
 248         svstate.vl = 6 # VL
 249         svstate.maxvl = 6 # MAXVL
 250         print ("SVSTATE", bin(svstate.asint()))
 251
 252         # copy before running
 253         expected_regs = deepcopy(initial_regs)
 254         for i in range(6):
 255             xi = i % 3
 256             yi = i // 3
 257             remap = yi+xi*2
 258             RA = initial_regs[0+idxs[remap]] # modulo 3 but still indexed
 259             RB = initial_regs[0+i]
 260             expected_regs[i+8] = RA+RB
 261             print ("expected", i, expected_regs[i+8])
 262
 263         with Program(lst, bigendian=False) as program:
 264             sim = self.run_tst_program(program, initial_regs, svstate=svstate)
 265
 266             print (sim.spr)
 267             SVSHAPE0 = sim.spr['SVSHAPE0']
 268             print ("SVSTATE after", bin(sim.svstate.asint()))
 269             print ("        vl", bin(sim.svstate.vl))
 270             print ("        mvl", bin(sim.svstate.maxvl))
 271             print ("    srcstep", bin(sim.svstate.srcstep))
 272             print ("    dststep", bin(sim.svstate.dststep))
 273             print ("      RMpst", bin(sim.svstate.RMpst))
 274             print ("       SVme", bin(sim.svstate.SVme))
 275             print ("        mo0", bin(sim.svstate.mo0))
 276             print ("        mo1", bin(sim.svstate.mo1))
 277             print ("        mi0", bin(sim.svstate.mi0))
 278             print ("        mi1", bin(sim.svstate.mi1))
 279             print ("        mi2", bin(sim.svstate.mi2))
 280             print ("STATE0svgpr", hex(SVSHAPE0.svgpr))
 281             print ("STATE0 xdim", SVSHAPE0.xdimsz)
 282             print ("STATE0 ydim", SVSHAPE0.ydimsz)
 283             print ("STATE0 skip", bin(SVSHAPE0.skip))
 284             print ("STATE0  inv", SVSHAPE0.invxyz)
 285             print ("STATE0order", SVSHAPE0.order)
 286             print (sim.gpr.dump())
 287             self.assertEqual(sim.svstate.RMpst, 0) # mm=0 so persist=0
 288             self.assertEqual(sim.svstate.SVme, 0b00001) # same as rmm
 289             # rmm is 0b00001 which means mi0=0 and all others inactive (0)
 290             self.assertEqual(sim.svstate.mi0, 0)
 291             self.assertEqual(sim.svstate.mi1, 0)
 292             self.assertEqual(sim.svstate.mi2, 0)
 293             self.assertEqual(sim.svstate.mo0, 0)
 294             self.assertEqual(sim.svstate.mo1, 0)
 295             self.assertEqual(SVSHAPE0.svgpr, 16) # SVG is shifted up by 1
 296             for i in range(1,4):
 297                 shape = sim.spr['SVSHAPE%d' % i]
 298                 self.assertEqual(shape.svgpr, 0)
 299             self._check_regs(sim, expected_regs)
 300
 301     def run_tst_program(self, prog, initial_regs=None,
 302                               svstate=None):
 303         if initial_regs is None:
 304             initial_regs = [0] * 32
 305         simulator = run_tst(prog, initial_regs, svstate=svstate)
 306         simulator.gpr.dump()
 307         return simulator
 308
 309
 310 if __name__ == "__main__":
 311     unittest.main()
 312