Merge branch 'pr' from nix-soc
[soc.git] / flake.nix
1 # The license for this file is included in the `nix` directory next to this file.
2
3 {
4 description = "FOSS CPU/GPU/VPU/SoC all in one, see https://libre-soc.org/";
5
6 inputs.nixpkgs.url = "github:L-as/nixpkgs?ref=libresoc"; # for alliance and migen
7 inputs.c4m-jtag.url = "git+https://git.libre-soc.org/git/c4m-jtag.git";
8 inputs.c4m-jtag.flake = false;
9 inputs.nmigen.url = "git+https://git.libre-soc.org/git/nmigen.git";
10 inputs.nmigen.flake = false;
11 inputs.nmigen-soc.url = "git+https://git.libre-soc.org/git/nmigen-soc.git";
12 inputs.nmigen-soc.flake = false;
13 inputs.migen.url = "github:m-labs/migen";
14 inputs.migen.flake = false;
15 inputs.yosys.url = "github:YosysHQ/yosys?rev=a58571d0fe8971cb7d3a619a31b2c21be6d75bac";
16 inputs.yosys.flake = false;
17 # submodules needed
18 inputs.nix-litex.url = "git+https://git.sr.ht/~lschuermann/nix-litex?ref=main";
19 inputs.nix-litex.flake = false;
20
21 outputs = { self, nixpkgs, c4m-jtag, nmigen, nmigen-soc, nix-litex, migen, yosys }:
22 let
23 getv = x: builtins.substring 0 8 x.lastModifiedDate;
24
25 supportedSystems = [ "x86_64-linux" "x86_64-darwin" "aarch64-linux" "aarch64-darwin" ];
26
27 forAllSystems = nixpkgs.lib.genAttrs supportedSystems;
28
29 litex = pkgs: import "${nix-litex}/pkgs" {
30 inherit pkgs;
31 pkgMetas = builtins.fromTOML (builtins.readFile ./nix/litex.toml);
32 skipChecks = true; # FIXME: remove once checks work
33 };
34
35 nixpkgsFor = forAllSystems (system: import nixpkgs { inherit system; overlays = [ self.overlay ]; });
36
37 lib = nixpkgs.lib;
38 in
39 {
40 overlay = final: prev: {
41 python37 = prev.python37.override {
42 packageOverrides = lib.composeExtensions (litex final).pythonOverlay (pfinal: pprev: {
43 libresoc-ieee754fpu = pfinal.callPackage ./nix/ieee754fpu.nix {};
44 libresoc-openpower-isa = pfinal.callPackage ./nix/openpower-isa.nix {};
45 c4m-jtag = pfinal.callPackage (import ./nix/c4m-jtag.nix { src = c4m-jtag; version = getv c4m-jtag; }) {};
46 bigfloat = pfinal.callPackage ./nix/bigfloat.nix {};
47 modgrammar = pfinal.callPackage ./nix/modgrammar.nix {};
48 libresoc-nmutil = pfinal.callPackage ./nix/nmutil.nix {};
49 libresoc-soc = pfinal.callPackage (import ./nix/soc.nix { version = getv self; }) {};
50
51 nmigen-soc = pprev.nmigen-soc.overrideAttrs (_: {
52 doCheck = false;
53 src = nmigen-soc;
54 setuptoolsCheckPhase = "true";
55 });
56
57 nmigen = pprev.nmigen.overrideAttrs (_: {
58 src = nmigen;
59 });
60
61 migen = pprev.migen.overrideAttrs (_: {
62 src = migen;
63 });
64 });
65 };
66
67 yosys = prev.yosys.overrideAttrs (_: {
68 version = "0.9+4052";
69 src = yosys;
70 });
71
72 libresoc-verilog = final.callPackage (import ./nix/verilog.nix { version = getv self; }) { python3Packages = final.python37Packages; };
73 libresoc-ls180 = final.callPackage (import ./nix/ls180.nix { version = getv self; }) { python3Packages = final.python37Packages; };
74 libresoc-ecp5 = final.callPackage (import ./nix/ecp5.nix { version = getv self; }) { python3Packages = final.python37Packages; };
75 libresoc-ecp5-program = final.callPackage (import ./nix/ecp5-program.nix { version = getv self; }) { python3Packages = final.python37Packages; };
76 libresoc-pinmux = final.callPackage (import ./nix/pinmux.nix { version = getv self; }) {};
77 };
78
79 apps = forAllSystems (system: {
80 ecp5 = {
81 type = "app";
82 program = "${nixpkgsFor.${system}.libresoc-ecp5-program}";
83 };
84 });
85 defaultApp = forAllSystems (system: self.apps.${system}.ecp5);
86
87 packages = forAllSystems (system: {
88 soc = nixpkgsFor.${system}.python37Packages.libresoc-soc;
89 verilog = nixpkgsFor.${system}.libresoc-verilog;
90 pinmux = nixpkgsFor.${system}.libresoc-pinmux;
91 ls180 = nixpkgsFor.${system}.libresoc-ls180;
92 ecp5 = nixpkgsFor.${system}.libresoc-ecp5;
93 ecp5-program = nixpkgsFor.${system}.libresoc-ecp5-program;
94 openpower-isa = nixpkgsFor.${system}.python37Packages.libresoc-openpower-isa;
95 debugNixpkgs = nixpkgsFor.${system};
96 });
97
98 defaultPackage = forAllSystems (system: self.packages.${system}.verilog);
99 };
100 }