src/TLB/test/test_tlb.py

   1 #import tracemalloc
   2 #tracemalloc.start()
   3
   4 from nmigen.compat.sim import run_simulation
   5
   6 from TLB.TLB import TLB
   7
   8 from TestUtil.test_helper import assert_op, assert_eq
   9
  10 #self.supermode = Signal(1) # Supervisor Mode
  11 #self.super_access = Signal(1) # Supervisor Access
  12 #self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
  13 #self.xwr = Signal(3) # Execute, Write, Read
  14 #self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
  15 #self.address_L1 = Signal(max=L1_size)
  16 #self.asid = Signal(asid_size) # Address Space IDentifier (ASID)
  17 #self.vma = Signal(vma_size) # Virtual Memory Address (VMA)
  18 #self.pte_in = Signal(pte_size) # To be saved Page Table Entry (PTE)
  19 #
  20 #self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  21 #self.perm_valid = Signal(1) # Denotes if the permissions are correct
  22 #self.pte_out = Signal(pte_size) # PTE that was mapped to by the VMA
  23
  24 COMMAND_READ=1
  25
  26 # Checks the data state of the CAM entry
  27 # Arguments:
  28 #   dut: The CamEntry being tested
  29 #   d (Data): The expected data
  30 #   op (Operation): (0 => ==), (1 => !=)
  31 def check_hit(dut, d):
  32     hit_d = yield dut.hit
  33     assert_eq("Data", hit_d, d)
  34
  35 def test_command(dut,cmd,xwr,cycles):
  36     yield dut.command.eq(cmd)
  37     yield dut.xwr.eq(xwr)
  38     for i in range(0,cycles):
  39         yield
  40
  41 def zero(dut):
  42     yield dut.supermode.eq(0)
  43     yield dut.super_access.eq(0)
  44     yield dut.mode.eq(0)
  45     yield dut.address_L1.eq(0)
  46     yield dut.asid.eq(0)
  47     yield dut.vma.eq(0)
  48     yield dut.pte_in.eq(0)
  49
  50 #TWO test cases: search, write_l1
  51
  52 def tbench(dut):
  53     #first set all signals to default values
  54     yield from zero(dut)
  55     yield from test_command(dut,COMMAND_READ,7,10)
  56     yield from check_hit(dut,0) #hit will be zero since there is no entry yet
  57     # TODO store an address
  58
  59
  60 def test_tlb():
  61     dut = TLB(15,36,64,8)
  62     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_tlb.vcd")
  63     print("TLB Unit Test WIP")
  64
  65 if __name__ == "__main__":
  66     test_tlb()