src/scoreboard/fu_dep_cell.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4 from nmutil.latch import SRLatch
   5
   6
   7 class FUDependenceCell(Elaboratable):
   8     """ implements 11.4.7 mitch alsup dependence cell, p27
   9     """
  10     def __init__(self):
  11         # inputs
  12         self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
  13         self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
  14         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  15
  16         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
  17         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
  18
  19         # outputs (latched rd/wr wait)
  20         self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
  21         self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         m.submodules.rd_l = rd_l = SRLatch(sync=False) # clock-sync'd
  26         m.submodules.wr_l = wr_l = SRLatch(sync=False) # clock-sync'd
  27
  28         # write latch: reset on go_wr HI, set on write waiting and issue
  29         m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
  30         m.d.comb += wr_l.r.eq(self.go_wr_i)
  31
  32         # read latch: reset on go_rd HI, set on read pending and issue
  33         m.d.comb += rd_l.s.eq(self.issue_i & self.rd_pend_i)
  34         m.d.comb += rd_l.r.eq(self.go_rd_i)
  35
  36         # Read/Write Pending Latches (read out horizontally)
  37         m.d.comb += self.wr_wait_o.eq(wr_l.q)
  38         m.d.comb += self.rd_wait_o.eq(rd_l.q)
  39
  40         return m
  41
  42     def __iter__(self):
  43         yield self.rd_pend_i
  44         yield self.wr_pend_i
  45         yield self.issue_i
  46         yield self.go_wr_i
  47         yield self.go_rd_i
  48         yield self.rd_wait_o
  49         yield self.wr_wait_o
  50
  51     def ports(self):
  52         return list(self)
  53
  54
  55 def dcell_sim(dut):
  56     yield dut.dest_i.eq(1)
  57     yield dut.issue_i.eq(1)
  58     yield
  59     yield dut.issue_i.eq(0)
  60     yield
  61     yield dut.src1_i.eq(1)
  62     yield dut.issue_i.eq(1)
  63     yield
  64     yield dut.issue_i.eq(0)
  65     yield
  66     yield dut.go_rd_i.eq(1)
  67     yield
  68     yield dut.go_rd_i.eq(0)
  69     yield
  70     yield dut.go_wr_i.eq(1)
  71     yield
  72     yield dut.go_wr_i.eq(0)
  73     yield
  74
  75 def test_dcell():
  76     dut = FUDependenceCell()
  77     vl = rtlil.convert(dut, ports=dut.ports())
  78     with open("test_fu_dcell.il", "w") as f:
  79         f.write(vl)
  80
  81     run_simulation(dut, dcell_sim(dut), vcd_name='test_fu_dcell.vcd')
  82
  83 if __name__ == '__main__':
  84     test_dcell()