src/scoreboard/fu_fu_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 #from nmutil.latch import SRLatch
   6 from .fu_dep_cell import FUDependenceCell
   7 from .fu_picker_vec import FU_Pick_Vec
   8
   9 """
  10
  11  6600 Function Unit Dependency Table Matrix inputs / outputs
  12  -----------------------------------------------------------
  13
  14 """
  15
  16 class FUFUDepMatrix(Elaboratable):
  17     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  18     """
  19     def __init__(self, n_fu_row, n_fu_col):
  20         self.n_fu_row = n_fu_row                  # Y (FU row#)   ^v
  21         self.n_fu_col = n_fu_col                # X (FU col #)  <>
  22         self.rd_pend_i = Signal(n_fu_row, reset_less=True) # Rd pending (left)
  23         self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
  24         self.issue_i = Signal(n_fu_col, reset_less=True)    # Issue in (top)
  25
  26         self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
  27         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  28
  29         # for Function Unit Readable/Writable (horizontal)
  30         self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
  31         self.writable_o = Signal(n_fu_col, reset_less=True) # writable (bot)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35
  36         # ---
  37         # matrix of dependency cells
  38         # ---
  39         dm = Array(Array(FUDependenceCell() for r in range(self.n_fu_row)) \
  40                                             for f in range(self.n_fu_col))
  41         for x in range(self.n_fu_col):
  42             for y in range(self.n_fu_row):
  43                 setattr(m.submodules, "dm_fx%d_fy%d" % (x, y), dm[x][y])
  44
  45         # ---
  46         # array of Function Unit Readable/Writable: row-length, horizontal
  47         # ---
  48         fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col))
  49         for x in range(self.n_fu_col):
  50             setattr(m.submodules, "fur_x%d" % (x), fur[x])
  51
  52         # ---
  53         # connect FU Readable/Writable vector
  54         # ---
  55         readable = []
  56         writable = []
  57         for x in range(self.n_fu_col):
  58             fu = fur[x]
  59             # accumulate Readable/Writable Vector outputs
  60             readable.append(fu.readable_o)
  61             writable.append(fu.writable_o)
  62
  63         # ... and output them from this module (horizontal, width=REGs)
  64         m.d.comb += self.readable_o.eq(Cat(*readable))
  65         m.d.comb += self.writable_o.eq(Cat(*writable))
  66
  67         # ---
  68         # connect FU Pending
  69         # ---
  70         for y in range(self.n_fu_row):
  71             fu = fur[x]
  72             rd_wait_o = []
  73             wr_wait_o = []
  74             for x in range(self.n_fu_col):
  75                 dc = dm[x][y]
  76                 # accumulate cell outputs rd/wr-pending
  77                 rd_wait_o.append(dc.rd_wait_o)
  78                 wr_wait_o.append(dc.wr_wait_o)
  79             # connect cell reg-select outputs to Reg Vector In
  80             m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
  81                          fu.wr_pend_i.eq(Cat(*wr_wait_o)),
  82                         ]
  83         # ---
  84         # connect Dependency Matrix issue to module issue
  85         # ---
  86         for y in range(self.n_fu_row):
  87             issue_i = []
  88             for x in range(self.n_fu_col):
  89                 dc = dm[x][y]
  90                 # accumulate cell inputs issue
  91                 issue_i.append(dc.issue_i)
  92             # wire up inputs from module to row cell inputs (Cat is gooood)
  93             m.d.comb += Cat(*issue_i).eq(self.issue_i)
  94
  95         # ---
  96         # connect Matrix go_rd_i/go_wr_i to module readable/writable
  97         # ---
  98         for x in range(self.n_fu_col):
  99             go_rd_i = []
 100             go_wr_i = []
 101             for y in range(self.n_fu_row):
 102                 dc = dm[x][y]
 103                 # accumulate cell go_rd/go_wr
 104                 go_rd_i.append(dc.go_rd_i)
 105                 go_wr_i.append(dc.go_wr_i)
 106             # wire up inputs from module to row cell inputs (Cat is gooood)
 107             m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 108                          Cat(*go_wr_i).eq(self.go_wr_i),
 109                         ]
 110
 111         # ---
 112         # connect Matrix pending
 113         # ---
 114         for y in range(self.n_fu_row):
 115             rd_pend_i = []
 116             wr_pend_i = []
 117             for x in range(self.n_fu_col):
 118                 dc = dm[x][y]
 119                 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
 120                 rd_pend_i.append(dc.rd_pend_i)
 121                 wr_pend_i.append(dc.wr_pend_i)
 122             # wire up inputs from module to row cell inputs (Cat is gooood)
 123             m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
 124                          Cat(*wr_pend_i).eq(self.wr_pend_i),
 125                         ]
 126
 127         return m
 128
 129     def __iter__(self):
 130         yield self.rd_pend_i
 131         yield self.wr_pend_i
 132         yield self.issue_i
 133         yield self.go_wr_i
 134         yield self.go_rd_i
 135         yield self.readable_o
 136         yield self.writable_o
 137
 138     def ports(self):
 139         return list(self)
 140
 141 def d_matrix_sim(dut):
 142     """ XXX TODO
 143     """
 144     yield dut.dest_i.eq(1)
 145     yield dut.issue_i.eq(1)
 146     yield
 147     yield dut.issue_i.eq(0)
 148     yield
 149     yield dut.src1_i.eq(1)
 150     yield dut.issue_i.eq(1)
 151     yield
 152     yield dut.issue_i.eq(0)
 153     yield
 154     yield dut.go_rd_i.eq(1)
 155     yield
 156     yield dut.go_rd_i.eq(0)
 157     yield
 158     yield dut.go_wr_i.eq(1)
 159     yield
 160     yield dut.go_wr_i.eq(0)
 161     yield
 162
 163 def test_fu_fu_matrix():
 164     dut = FUFUDepMatrix(n_fu_row=3, n_fu_col=4)
 165     vl = rtlil.convert(dut, ports=dut.ports())
 166     with open("test_fu_fu_matrix.il", "w") as f:
 167         f.write(vl)
 168
 169     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_fu_matrix.vcd')
 170
 171 if __name__ == '__main__':
 172     test_fu_fu_matrix()