src/scoreboard/shadow_fn.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Cat, Elaboratable
   4 from nmutil.latch import SRLatch
   5 from nmigen.lib.coding import Decoder
   6
   7
   8 class ShadowFn(Elaboratable):
   9     """ implements shadowing 11.5.1, p55, just the individual shadow function
  10     """
  11     def __init__(self):
  12
  13         # inputs
  14         self.issue_i = Signal(reset_less=True)
  15         self.shadow_i  = Signal(reset_less=True)
  16         self.s_fail_i  = Signal(reset_less=True)
  17         self.s_good_i  = Signal(reset_less=True)
  18
  19         # outputs
  20         self.shadow_o = Signal(reset_less=True)
  21         self.recover_o = Signal(reset_less=True)
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         m.submodules.sl = sl = SRLatch(sync=False)
  26
  27         m.d.comb += sl.s.eq(self.shadow_i & self.issue_i)
  28         m.d.comb += sl.r.eq(self.s_good_i)
  29         m.d.comb += self.recover_o.eq(sl.q & self.s_fail_i)
  30         m.d.comb += self.shadow_o.eq(sl.q)
  31
  32         return m
  33
  34     def __iter__(self):
  35         yield self.issue_i
  36         yield self.shadow_i
  37         yield self.s_fail_i
  38         yield self.s_good_i
  39         yield self.shadow_o
  40         yield self.recover_o
  41
  42     def ports(self):
  43         return list(self)
  44
  45
  46 def shadow_fn_unit_sim(dut):
  47     yield dut.dest_i.eq(1)
  48     yield dut.issue_i.eq(1)
  49     yield
  50     yield dut.issue_i.eq(0)
  51     yield
  52     yield dut.src1_i.eq(1)
  53     yield dut.issue_i.eq(1)
  54     yield
  55     yield
  56     yield
  57     yield dut.issue_i.eq(0)
  58     yield
  59     yield dut.go_rd_i.eq(1)
  60     yield
  61     yield dut.go_rd_i.eq(0)
  62     yield
  63     yield dut.go_wr_i.eq(1)
  64     yield
  65     yield dut.go_wr_i.eq(0)
  66     yield
  67
  68
  69 def test_shadow_fn_unit():
  70     dut = ShadowFn()
  71     vl = rtlil.convert(dut, ports=dut.ports())
  72     with open("test_shadow_fn_unit.il", "w") as f:
  73         f.write(vl)
  74
  75     run_simulation(dut, shadow_fn_unit_sim(dut),
  76                    vcd_name='test_shadow_fn_unit.vcd')
  77
  78 if __name__ == '__main__':
  79     test_shadow_fn_unit()