src/scoreboard/shadow_fn.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Cat, Elaboratable
   4 from nmutil.latch import SRLatch
   5
   6
   7 class ShadowFn(Elaboratable):
   8     """ implements shadowing 11.5.1, p55, just the individual shadow function
   9     """
  10     def __init__(self):
  11
  12         # inputs
  13         self.issue_i = Signal(reset_less=True)
  14         self.shadow_i  = Signal(reset_less=True)
  15         self.s_fail_i  = Signal(reset_less=True)
  16         self.s_good_i  = Signal(reset_less=True)
  17
  18         # outputs
  19         self.shadow_o = Signal(reset_less=True)
  20         self.recover_o = Signal(reset_less=True)
  21
  22     def elaborate(self, platform):
  23         m = Module()
  24         m.submodules.sl = sl = SRLatch(sync=False)
  25
  26         m.d.comb += sl.s.eq(self.shadow_i & self.issue_i)
  27         m.d.comb += sl.r.eq(self.s_good_i)
  28         m.d.comb += self.recover_o.eq(sl.q & self.s_fail_i)
  29         m.d.comb += self.shadow_o.eq(sl.q)
  30
  31         return m
  32
  33     def __iter__(self):
  34         yield self.issue_i
  35         yield self.shadow_i
  36         yield self.s_fail_i
  37         yield self.s_good_i
  38         yield self.shadow_o
  39         yield self.recover_o
  40
  41     def ports(self):
  42         return list(self)
  43
  44
  45 def shadow_fn_unit_sim(dut):
  46     yield dut.dest_i.eq(1)
  47     yield dut.issue_i.eq(1)
  48     yield
  49     yield dut.issue_i.eq(0)
  50     yield
  51     yield dut.src1_i.eq(1)
  52     yield dut.issue_i.eq(1)
  53     yield
  54     yield
  55     yield
  56     yield dut.issue_i.eq(0)
  57     yield
  58     yield dut.go_rd_i.eq(1)
  59     yield
  60     yield dut.go_rd_i.eq(0)
  61     yield
  62     yield dut.go_wr_i.eq(1)
  63     yield
  64     yield dut.go_wr_i.eq(0)
  65     yield
  66
  67
  68 def test_shadow_fn_unit():
  69     dut = ShadowFn()
  70     vl = rtlil.convert(dut, ports=dut.ports())
  71     with open("test_shadow_fn_unit.il", "w") as f:
  72         f.write(vl)
  73
  74     run_simulation(dut, shadow_fn_unit_sim(dut),
  75                    vcd_name='test_shadow_fn_unit.vcd')
  76
  77 if __name__ == '__main__':
  78     test_shadow_fn_unit()