src/soc/alu/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.selectable_int import SelectableInt
  10 from soc.simulator.program import Program
  11 from soc.decoder.isa.all import ISA
  12
  13
  14 from soc.alu.pipeline import ALUBasePipe
  15 from soc.alu.alu_input_record import CompALUOpSubset
  16 from soc.alu.pipe_data import ALUPipeSpec
  17 import random
  18
  19 def get_rec_width(rec):
  20     recwidth = 0
  21     # Setup random inputs for dut.op
  22     for p in rec.ports():
  23         width = p.width
  24         recwidth += width
  25     return recwidth
  26
  27
  28
  29 class ALUTestCase(FHDLTestCase):
  30     def run_tst(self, program, initial_regs):
  31         m = Module()
  32         comb = m.d.comb
  33         instruction = Signal(32)
  34
  35         pdecode = create_pdecode()
  36
  37         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  38
  39         rec = CompALUOpSubset()
  40
  41         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
  42         m.submodules.alu = alu = ALUBasePipe(pspec)
  43
  44         comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
  45         comb += alu.p.data_i.a.eq(initial_regs[1])
  46         comb += alu.p.data_i.b.eq(initial_regs[2])
  47         comb += alu.p.valid_i.eq(1)
  48         comb += alu.n.ready_i.eq(1)
  49         simulator = ISA(pdecode2, initial_regs)
  50         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  51         sim = Simulator(m)
  52         gen = program.generate_instructions()
  53
  54         sim.add_clock(1e-6)
  55         def process():
  56             instructions = list(zip(gen, program.assembly.splitlines()))
  57
  58             index = simulator.pc.CIA.value//4
  59             while index < len(instructions):
  60                 ins, code = instructions[index]
  61
  62                 print("0x{:X}".format(ins & 0xffffffff))
  63                 print(code)
  64
  65                 # ask the decoder to decode this binary data (endian'd)
  66                 yield pdecode2.dec.bigendian.eq(0)  # little / big?
  67                 yield instruction.eq(ins)          # raw binary instr.
  68                 yield
  69                 opname = code.split(' ')[0]
  70                 yield from simulator.call(opname)
  71                 index = simulator.pc.CIA.value//4
  72
  73                 vld = yield alu.n.valid_o
  74                 while not vld:
  75                     yield
  76                     vld = yield alu.n.valid_o
  77                 yield
  78                 alu_out = yield alu.n.data_o.o
  79                 self.assertEqual(simulator.gpr(3).value, alu_out)
  80
  81         sim.add_sync_process(process)
  82         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  83                            traces=[]):
  84             sim.run()
  85         return simulator
  86
  87     def run_tst_program(self, prog, initial_regs=[0] * 32):
  88         simulator = self.run_tst(prog, initial_regs)
  89         simulator.gpr.dump()
  90         return simulator
  91
  92     def test_rand(self):
  93         insns = ["add", "add.", "and", "or", "xor", "subf"]
  94         for i in range(40):
  95             choice = random.choice(insns)
  96             lst = [f"{choice} 3, 1, 2"]
  97             initial_regs = [0] * 32
  98             initial_regs[1] = random.randint(0, (1<<64)-1)
  99             initial_regs[2] = random.randint(0, (1<<64)-1)
 100             with Program(lst) as program:
 101                 sim = self.run_tst_program(program, initial_regs)
 102
 103     def test_rand_imm(self):
 104         insns = ["addi", "addis", "subfic"]
 105         for i in range(10):
 106             choice = random.choice(insns)
 107             imm = random.randint(-(1<<15), (1<<15)-1)
 108             lst = [f"{choice} 3, 1, {imm}"]
 109             print(lst)
 110             initial_regs = [0] * 32
 111             initial_regs[1] = random.randint(0, (1<<64)-1)
 112             with Program(lst) as program:
 113                 sim = self.run_tst_program(program, initial_regs)
 114
 115     def test_rand_imm_logical(self):
 116         insns = ["andi.", "andis.", "ori", "oris", "xori", "xoris"]
 117         for i in range(10):
 118             choice = random.choice(insns)
 119             imm = random.randint(0, (1<<16)-1)
 120             lst = [f"{choice} 3, 1, {imm}"]
 121             print(lst)
 122             initial_regs = [0] * 32
 123             initial_regs[1] = random.randint(0, (1<<64)-1)
 124             with Program(lst) as program:
 125                 sim = self.run_tst_program(program, initial_regs)
 126
 127     def test_shift(self):
 128         insns = ["slw", "sld"]
 129         for i in range(10):
 130             choice = random.choice(insns)
 131             lst = [f"{choice} 3, 1, 2"]
 132             initial_regs = [0] * 32
 133             initial_regs[1] = random.randint(0, (1<<64)-1)
 134             initial_regs[2] = random.randint(0, 63)
 135             print(initial_regs[1], initial_regs[2])
 136             with Program(lst) as program:
 137                 sim = self.run_tst_program(program, initial_regs)
 138
 139     @unittest.skip("broken")
 140     def test_ilang(self):
 141         rec = CompALUOpSubset()
 142
 143         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
 144         alu = ALUBasePipe(pspec)
 145         vl = rtlil.convert(alu, ports=[])
 146         with open("pipeline.il", "w") as f:
 147             f.write(vl)
 148
 149 if __name__ == "__main__":
 150     unittest.main()