src/soc/consts.py

   1 # sigh create little-ended versions of bitfield flags
   2 def botchify(bekls, lekls):
   3     for attr in dir(bekls):
   4         if attr[0] == '_':
   5             continue
   6         setattr(lekls, attr, 63-getattr(bekls, attr))
   7
   8
   9 # Can't think of a better place to put these functions.
  10 # Return an arbitrary subfield of a larger field.
  11 def field_slice(msb0_start, msb0_end, field_width=64):
  12     """Answers with a subfield slice of the signal r ("register"),
  13     where the start and end bits use IBM conventions.  msb0_start < msb0_end.
  14     The range specified is inclusive on both ends.
  15     field_width specifies the total number of bits (not bits-1)
  16     """
  17     if msb0_start >= msb0_end:
  18         raise ValueError(
  19             "start ({}) must be less than end ({})".format(start, end)
  20         )
  21     # sigh.  MSB0 (IBM numbering) is inverted.  converting to python
  22     # we *swap names* so as not to get confused by having "end, start"
  23     end = (field_width-1) - msb0_start
  24     start = (field_width-1) - msb0_end
  25
  26     return slice(start, end + 1)
  27
  28
  29 def field(r, start, end=None):
  30     """Answers with a subfield of the signal r ("register"), where
  31     the start and end bits use IBM conventions.  start < end, if
  32     end is provided.  The range specified is inclusive on both ends.
  33     """
  34     if end is None:
  35         return r[63 - start]
  36     else:
  37         return r[field_slice(start, end)]
  38
  39
  40 # Listed in V3.0B Book III Chap 4.2.1
  41 # MSR bit numbers, *bigendian* order (PowerISA format)
  42 # use this in the simulator
  43 class MSRb:
  44     SF  = 0     # Sixty-Four bit mode
  45     HV  = 3     # Hypervisor state
  46     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
  47     TSs = 29    # Transactional State (subfield)
  48     TSe = 30    # Transactional State (subfield)
  49     TM  = 31    # Transactional Memory Available
  50     VEC = 38    # Vector Available
  51     VSX = 40    # VSX Available
  52     S   = 41    # Secure state
  53     EE  = 48    # External interrupt Enable
  54     PR  = 49    # PRoblem state
  55     FP  = 50    # FP available
  56     ME  = 51    # Machine Check int enable
  57     FE0 = 52    # Floating-Point Exception Mode 0
  58     TEs = 53    # Trace Enable (subfield)
  59     TEe = 54    # Trace Enable (subfield)
  60     FE1 = 55    # Floating-Point Exception Mode 1
  61     IR  = 58    # Instruction Relocation
  62     DR  = 59    # Data Relocation
  63     PMM = 60    # Performance Monitor Mark
  64     RI  = 62    # Recoverable Interrupt
  65     LE  = 63    # Little Endian
  66
  67 # use this inside the HDL (where everything is little-endian)
  68 class MSR:
  69     pass
  70
  71 botchify(MSRb, MSR)
  72
  73 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  74
  75 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
  76 # (TODO: add more?)
  77 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  78 # to expand traptype to cope with the increased range
  79
  80 # use this in the simulator
  81 class PIb:
  82     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
  83     FP           = 43    # 1 if FP exception
  84     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
  85     PRIV         = 45    # 1 if privileged interrupt
  86     TRAP         = 46    # 1 if exception is "trap" type
  87     ADR          = 47    # 0 if SRR0 = address of instruction causing exception
  88
  89 # and use this in the HDL
  90 class PI:
  91     pass
  92
  93 botchify(PIb, PI)
  94
  95 # see traptype (and trap main_stage.py)
  96 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  97 # to expand traptype to cope with the increased range
  98
  99 class TT:
 100     FP = 1<<0
 101     PRIV = 1<<1
 102     TRAP = 1<<2
 103     ADDR = 1<<3
 104     ILLEG = 1<<4 # currently the max, therefore traptype must be 5 bits
 105     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
 106     size = 5 # MUST update this to contain the full number of Trap Types