src/soc/consts.py

   1 # Listed in V3.0B Book III Chap 4.2.1
   2 # MSR bit numbers
   3
   4 class MSR:
   5     SF  = (63 - 0)     # Sixty-Four bit mode
   6     HV  = (63 - 3)     # Hypervisor state
   7     UND = (63 - 5)     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
   8     TSs = (63 - 29)    # Transactional State (subfield)
   9     TSe = (63 - 30)    # Transactional State (subfield)
  10     TM  = (63 - 31)    # Transactional Memory Available
  11     VEC = (63 - 38)    # Vector Available
  12     VSX = (63 - 40)    # VSX Available
  13     S   = (63 - 41)    # Secure state
  14     EE  = (63 - 48)    # External interrupt Enable
  15     PR  = (63 - 49)    # PRoblem state
  16     FP  = (63 - 50)    # FP available
  17     ME  = (63 - 51)    # Machine Check int enable
  18     FE0 = (63 - 52)    # Floating-Point Exception Mode 0
  19     TEs = (63 - 53)    # Trace Enable (subfield)
  20     TEe = (63 - 54)    # Trace Enable (subfield)
  21     FE1 = (63 - 55)    # Floating-Point Exception Mode 1
  22     IR  = (63 - 58)    # Instruction Relocation
  23     DR  = (63 - 59)    # Data Relocation
  24     PMM = (63 - 60)    # Performance Monitor Mark
  25     RI  = (63 - 62)    # Recoverable Interrupt
  26     LE  = (63 - 63)    # Little Endian
  27
  28 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  29
  30 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
  31 # (TODO: add more?)
  32 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  33 # to expand traptype to cope with the increased range
  34
  35 class PI:
  36     TM_BAD_THING = (63 - 42) # 1 for a TM Bad Thing type interrupt
  37     FP    = (63 - 43)    # 1 if FP exception
  38     ILLEG = (63 - 44)    # 1 if illegal instruction (not doing hypervisor)
  39     PRIV  = (63 - 45)    # 1 if privileged interrupt
  40     TRAP  = (63 - 46)    # 1 if exception is "trap" type
  41     ADR   = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
  42
  43 # see traptype (and trap main_stage.py)
  44 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
  45 # to expand traptype to cope with the increased range
  46
  47 class TT:
  48     FP = 1<<0
  49     PRIV = 1<<1
  50     TRAP = 1<<2
  51     ADDR = 1<<3
  52     ILLEG = 1<<4 # currently the max, therefore traptype must be 5 bits