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fix bug in radixmmu.py
[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 """
69 Get Root Page
70
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
73 // PTCR Layout
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
78 // 0 4 51 52 58 59 63
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
84 //
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
86 //
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
90 //
91 // Partition Table
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
95 // | | |
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 // | | | <-- effLPID
100 // |----------------------|----------------------|
101 // .
102 // .
103 // .
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 //
108 // The effective LPID forms the index into the Partition Table.
109 //
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
112 //
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
114 //
115 // PATE0 Layout
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
120 //
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
125 //
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
129 // Note: RPDS >= 5.
130 //
131 // PATE1 Layout
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
136 //
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
141 // Note: PRTS <= 24.
142 //
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
146 // be zero.
147
148
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
150 //
151 // Process Table
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
155 // | | |
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 // | | | <-- effPID
160 // |----------------------|----------------------|
161 // .
162 // .
163 // .
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 //
168 // The effective Process id (PID) forms the index into the Process Table.
169 //
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
172 //
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
174 //
175 // PRTE0 Layout
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
180 //
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
185 //
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
189 // Note: RPDS >= 5.
190 //
191 // PRTE1 Layout
192 // -----------------------------------------------
193 // | /// |
194 // -----------------------------------------------
195 // 0 63
196 // All bits are reserved.
197
198
199 """
200
201 testmem = {
202
203 0x10000: # PARTITION_TABLE_2 (not implemented yet)
204 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
205 0x800000000100000b,
206
207 0x30000: # RADIX_ROOT_PTE
208 # V = 1 L = 0 NLB = 0x400 NLS = 9
209 0x8000000000040009,
210 0x40000: # RADIX_SECOND_LEVEL
211 # V = 1 L = 1 SW = 0 RPN = 0
212 # R = 1 C = 1 ATT = 0 EAA 0x7
213 0xc000000000000187,
214
215 0x1000000: # PROCESS_TABLE_3
216 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
217 0x40000000000300ad,
218 }
219
220 # this one has a 2nd level RADIX with a RPN of 0x5000
221 testmem2 = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0x5000
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000005000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240 #def pt_RTS1(x):
241 # return x
242 def pt_RPDB(x):
243 return x[8:56]
244 #def pt_RTS2(x):
245 # return x
246 #def pt_RPDS(x):
247 # return x
248
249
250 testresult = """
251 prtbl = 1000000
252 DCACHE GET 1000000 PROCESS_TABLE_3
253 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
254 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
255 DCACHE GET 10000 PARTITION_TABLE_2
256 translated done 1 err 0 badtree 0 addr 40000 pte 0
257 """
258
259 # see qemu/target/ppc/mmu-radix64.c for reference
260 class RADIX:
261 def __init__(self, mem, caller):
262 self.mem = mem
263 self.caller = caller
264 if caller is not None:
265 self.dsisr = self.caller.spr["DSISR"]
266 self.dar = self.caller.spr["DAR"]
267 self.pidr = self.caller.spr["PIDR"]
268 self.prtbl = self.caller.spr["PRTBL"]
269 self.msr = self.caller.msr
270
271 # cached page table stuff
272 self.pgtbl0 = 0
273 self.pt0_valid = False
274 self.pgtbl3 = 0
275 self.pt3_valid = False
276
277 def __call__(self, addr, sz):
278 val = self.ld(addr.value, sz, swap=False)
279 print("RADIX memread", addr, sz, val)
280 return SelectableInt(val, sz*8)
281
282 def ld(self, address, width=8, swap=True, check_in_mem=False,
283 instr_fetch=False):
284 print("RADIX: ld from addr 0x%x width %d" % (address, width))
285
286 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
287 if instr_fetch:
288 mode = 'EXECUTE'
289 else:
290 mode = 'LOAD'
291 addr = SelectableInt(address, 64)
292 (shift, mbits, pgbase) = self._decode_prte(addr)
293 #shift = SelectableInt(0, 32)
294
295 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
296
297 # use pte to load from phys address
298 return self.mem.ld(pte.value, width, swap, check_in_mem)
299
300 # XXX set SPRs on error
301
302 # TODO implement
303 def st(self, address, v, width=8, swap=True):
304 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
305
306 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
307 mode = 'STORE'
308 addr = SelectableInt(address, 64)
309 (shift, mbits, pgbase) = self._decode_prte(addr)
310 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
311
312 # use pte to store at phys address
313 return self.mem.st(pte.value, v, width, swap)
314
315 # XXX set SPRs on error
316
317 def memassign(self, addr, sz, val):
318 print("memassign", addr, sz, val)
319 self.st(addr.value, val.value, sz, swap=False)
320
321 def _next_level(self, addr, entry_width, swap, check_in_mem):
322 # implement read access to mmu mem here
323
324 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
325 value = self.mem.ld(addr.value, 8, False, check_in_mem)
326 assert(value is not None, "address lookup %x not found" % addr.value)
327
328 print("addr", hex(addr.value))
329 data = SelectableInt(value, 64) # convert to SelectableInt
330 print("value", hex(value))
331 # index += 1
332 return data;
333
334 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
335 """walk tree
336
337 // vaddr 64 Bit
338 // vaddr |-----------------------------------------------------|
339 // | Unused | Used |
340 // |-----------|-----------------------------------------|
341 // | 0000000 | usefulBits = X bits (typically 52) |
342 // |-----------|-----------------------------------------|
343 // | |<--Cursize---->| |
344 // | | Index | |
345 // | | into Page | |
346 // | | Directory | |
347 // |-----------------------------------------------------|
348 // | |
349 // V |
350 // PDE |---------------------------| |
351 // |V|L|//| NLB |///|NLS| |
352 // |---------------------------| |
353 // PDE = Page Directory Entry |
354 // [0] = V = Valid Bit |
355 // [1] = L = Leaf bit. If 0, then |
356 // [4:55] = NLB = Next Level Base |
357 // right shifted by 8 |
358 // [59:63] = NLS = Next Level Size |
359 // | NLS >= 5 |
360 // | V
361 // | |--------------------------|
362 // | | usfulBits = X-Cursize |
363 // | |--------------------------|
364 // |---------------------><--NLS-->| |
365 // | Index | |
366 // | into | |
367 // | PDE | |
368 // |--------------------------|
369 // |
370 // If the next PDE obtained by |
371 // (NLB << 8 + 8 * index) is a |
372 // nonleaf, then repeat the above. |
373 // |
374 // If the next PDE is a leaf, |
375 // then Leaf PDE structure is as |
376 // follows |
377 // |
378 // |
379 // Leaf PDE |
380 // |------------------------------| |----------------|
381 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
382 // |------------------------------| |----------------|
383 // [0] = V = Valid Bit |
384 // [1] = L = Leaf Bit = 1 if leaf |
385 // PDE |
386 // [2] = Sw = Sw bit 0. |
387 // [7:51] = RPN = Real Page Number, V
388 // real_page = RPN << 12 -------------> Logical OR
389 // [52:54] = Sw Bits 1:3 |
390 // [55] = R = Reference |
391 // [56] = C = Change V
392 // [58:59] = Att = Physical Address
393 // 0b00 = Normal Memory
394 // 0b01 = SAO
395 // 0b10 = Non Idenmpotent
396 // 0b11 = Tolerant I/O
397 // [60:63] = Encoded Access
398 // Authority
399 //
400 """
401 # get sprs
402 print("_walk_tree")
403 pidr = self.caller.spr["PIDR"]
404 prtbl = self.caller.spr["PRTBL"]
405 print(pidr)
406 print(prtbl)
407 p = addr[55:63]
408 print("last 8 bits ----------")
409 print
410
411 # get address of root entry
412 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
413 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
414 print("starting with prtable, addr_next",addr_next)
415
416 assert(addr_next.bits == 64)
417 assert(addr_next.value == 0x1000000) #TODO
418
419 # read an entry from prtable
420 swap = False
421 check_in_mem = False
422 entry_width = 8
423 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
424 print("pr_table",data)
425 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
426
427 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
428 shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
429 assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
430 print("shift",shift)
431
432 # mbits := unsigned('0' & data(4 downto 0));
433 mbits = selectconcat(SelectableInt(0,1), data[58:63])
434 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
435
436 # WIP
437 if mbits==0:
438 return "invalid"
439
440 # mask_size := mbits(4 downto 0);
441 mask_size = mbits[0:5];
442 assert(mask_size.bits==5)
443 print("before segment check ==========")
444 print("mask_size:",bin(mask_size.value))
445 print("mbits:",bin(mbits.value))
446
447 print("calling segment_check")
448
449 mbits = selectconcat(SelectableInt(0,1), mask_size)
450 shift = self._segment_check(addr, mbits, shift)
451 print("shift",shift)
452
453 # v.pgbase := pgtbl(55 downto 8) & x"00";
454 zero8 = SelectableInt(0,8)
455
456 rtdb = pt_RPDB(pgtbl)
457 print("rtdb",rtdb)
458 pgbase = selectconcat(zero8,rtdb,zero8)
459 print("pgbase",pgbase)
460 # assert(pgbase.value==0x30000)
461
462 addrsh = addrshift(addr,shift)
463 print("addrsh",addrsh)
464
465 #print("========================")
466 #print("should be",bin(0x30000))
467 #print("pgbase",bin(pgbase.value))
468 #print("addrsh",bin(addrsh.value))
469
470
471 addr_next = self._get_pgtable_addr(mask_size, pgbase, addrsh)
472 print("DONE addr_next",addr_next)
473
474 # wrong '0b000000011000000000'
475 # right '0b110000000000000000'
476 assert(addr_next==0x30000)
477
478 # walk tree starts on prtbl
479 while True:
480 print("nextlevel----------------------------")
481 # read an entry
482 swap = False
483 check_in_mem = False
484 entry_width = 8
485
486 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
487 valid = rpte_valid(data)
488 leaf = rpte_leaf(data)
489
490 print(" valid, leaf", valid, leaf)
491 if not valid:
492 return "invalid" # TODO: return error
493 if leaf:
494 print ("is leaf, checking perms")
495 ok = self._check_perms(data, priv, mode)
496 if ok == True: # data was ok, found phys address, return it?
497 paddr = self._get_pte(addrsh, addr, data)
498 print (" phys addr", hex(paddr.value))
499 return paddr
500 return ok # return the error code
501 else:
502 newlookup = self._new_lookup(data, shift)
503 if newlookup == 'badtree':
504 return newlookup
505 shift, mask, pgbase = newlookup
506 print (" next level", shift, mask, pgbase)
507 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
508 print("calling _get_pgtable_addr")
509 print(mask) #SelectableInt(value=0x9, bits=4)
510 print(pgbase) #SelectableInt(value=0x40000, bits=56)
511 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
512 pgbase = SelectableInt(pgbase.value, 64)
513 addrsh = addrshift(addr,shift)
514 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
515 print("addr_next",addr_next)
516 print("addrsh",addrsh)
517
518 def _new_lookup(self, data, shift):
519 """
520 mbits := unsigned('0' & data(4 downto 0));
521 if mbits < 5 or mbits > 16 or mbits > r.shift then
522 v.state := RADIX_FINISH;
523 v.badtree := '1'; -- throw error
524 else
525 v.shift := v.shift - mbits;
526 v.mask_size := mbits(4 downto 0);
527 v.pgbase := data(55 downto 8) & x"00"; NLB?
528 v.state := RADIX_LOOKUP; --> next level
529 end if;
530 """
531 mbits = data[59:64]
532 print("mbits=", mbits)
533 if mbits < 5 or mbits > 16: #fixme compare with r.shift
534 print("badtree")
535 return "badtree"
536 # reduce shift (has to be done at same bitwidth)
537 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
538 mask_size = mbits[1:5] # get 4 LSBs
539 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
540 return shift, mask_size, pgbase
541
542 def _decode_prte(self, data):
543 """PRTE0 Layout
544 -----------------------------------------------
545 |/|RTS1|/| RPDB | RTS2 | RPDS |
546 -----------------------------------------------
547 0 1 2 3 4 55 56 58 59 63
548 """
549 # note that SelectableInt does big-endian! so the indices
550 # below *directly* match the spec, unlike microwatt which
551 # has to turn them around (to LE)
552 zero = SelectableInt(0, 1)
553 rts = selectconcat(zero,
554 data[56:59], # RTS2
555 data[1:3], # RTS1
556 )
557 masksize = data[59:64] # RPDS
558 mbits = selectconcat(zero, masksize)
559 pgbase = selectconcat(data[8:56], # part of RPDB
560 SelectableInt(0, 16),)
561
562 return (rts, mbits, pgbase)
563
564 def _segment_check(self, addr, mbits, shift):
565 """checks segment valid
566 mbits := '0' & r.mask_size;
567 v.shift := r.shift + (31 - 12) - mbits;
568 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
569 if r.addr(63) /= r.addr(62) or nonzero = '1' then
570 v.state := RADIX_FINISH;
571 v.segerror := '1';
572 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
573 v.state := RADIX_FINISH;
574 v.badtree := '1';
575 else
576 v.state := RADIX_LOOKUP;
577 """
578 # note that SelectableInt does big-endian! so the indices
579 # below *directly* match the spec, unlike microwatt which
580 # has to turn them around (to LE)
581 mask = genmask(shift, 44)
582 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
583 print ("RADIX _segment_check nonzero", bin(nonzero.value))
584 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
585 if addr[0] != addr[1] or nonzero != 0:
586 return "segerror"
587 limit = shift + (31 - 12)
588 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
589 return "badtree mbits="+str(mbits.value)+" limit="+str(limit.value)
590 new_shift = shift + (31 - 12) - mbits
591 # TODO verify that returned result is correct
592 return new_shift
593
594 def _check_perms(self, data, priv, mode):
595 """check page permissions
596 // Leaf PDE |
597 // |------------------------------| |----------------|
598 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
599 // |------------------------------| |----------------|
600 // [0] = V = Valid Bit |
601 // [1] = L = Leaf Bit = 1 if leaf |
602 // PDE |
603 // [2] = Sw = Sw bit 0. |
604 // [7:51] = RPN = Real Page Number, V
605 // real_page = RPN << 12 -------------> Logical OR
606 // [52:54] = Sw Bits 1:3 |
607 // [55] = R = Reference |
608 // [56] = C = Change V
609 // [58:59] = Att = Physical Address
610 // 0b00 = Normal Memory
611 // 0b01 = SAO
612 // 0b10 = Non Idenmpotent
613 // 0b11 = Tolerant I/O
614 // [60:63] = Encoded Access
615 // Authority
616 //
617 -- test leaf bit
618 -- check permissions and RC bits
619 perm_ok := '0';
620 if r.priv = '1' or data(3) = '0' then
621 if r.iside = '0' then
622 perm_ok := data(1) or (data(2) and not r.store);
623 else
624 -- no IAMR, so no KUEP support for now
625 -- deny execute permission if cache inhibited
626 perm_ok := data(0) and not data(5);
627 end if;
628 end if;
629 rc_ok := data(8) and (data(7) or not r.store);
630 if perm_ok = '1' and rc_ok = '1' then
631 v.state := RADIX_LOAD_TLB;
632 else
633 v.state := RADIX_FINISH;
634 v.perm_err := not perm_ok;
635 -- permission error takes precedence over RC error
636 v.rc_error := perm_ok;
637 end if;
638 """
639 # decode mode into something that matches microwatt equivalent code
640 instr_fetch, store = 0, 0
641 if mode == 'STORE':
642 store = 1
643 if mode == 'EXECUTE':
644 inst_fetch = 1
645
646 # check permissions and RC bits
647 perm_ok = 0
648 if priv == 1 or data[60] == 0:
649 if instr_fetch == 0:
650 perm_ok = data[62] | (data[61] & (store == 0))
651 # no IAMR, so no KUEP support for now
652 # deny execute permission if cache inhibited
653 perm_ok = data[63] & ~data[58]
654 rc_ok = data[55] & (data[56] | (store == 0))
655 if perm_ok == 1 and rc_ok == 1:
656 return True
657
658 return "perm_err" if perm_ok == 0 else "rc_err"
659
660 def _get_prtable_addr(self, shift, prtbl, addr, pid):
661 """
662 if r.addr(63) = '1' then
663 effpid := x"00000000";
664 else
665 effpid := r.pid;
666 end if;
667 x"00" & r.prtbl(55 downto 36) &
668 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
669 (effpid(31 downto 8) and finalmask(23 downto 0))) &
670 effpid(7 downto 0) & "0000";
671 """
672 print ("_get_prtable_addr", shift, prtbl, addr, pid)
673 finalmask = genmask(shift, 44)
674 finalmask24 = finalmask[20:44]
675 if addr[0].value == 1:
676 effpid = SelectableInt(0, 32)
677 else:
678 effpid = pid #self.pid # TODO, check on this
679 zero8 = SelectableInt(0, 8)
680 zero4 = SelectableInt(0, 4)
681 res = selectconcat(zero8,
682 prtbl[8:28], #
683 (prtbl[28:52] & ~finalmask24) | #
684 (effpid[0:24] & finalmask24), #
685 effpid[24:32],
686 zero4
687 )
688 return res
689
690 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
691 """
692 x"00" & r.pgbase(55 downto 19) &
693 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
694 "000";
695 """
696 mask16 = genmask(mask_size+5, 16)
697 zero8 = SelectableInt(0, 8)
698 zero3 = SelectableInt(0, 3)
699 res = selectconcat(zero8,
700 pgbase[8:45], #
701 (pgbase[45:61] & ~mask16) | #
702 (addrsh & mask16), #
703 zero3
704 )
705 return res
706
707 def _get_pte(self, shift, addr, pde):
708 """
709 x"00" &
710 ((r.pde(55 downto 12) and not finalmask) or
711 (r.addr(55 downto 12) and finalmask))
712 & r.pde(11 downto 0);
713 """
714 shift.value = 12
715 finalmask = genmask(shift, 44)
716 zero8 = SelectableInt(0, 8)
717 rpn = pde[8:52] # RPN = Real Page Number
718 abits = addr[8:52] # non-masked address bits
719 print(" get_pte RPN", hex(rpn.value))
720 print(" abits", hex(abits.value))
721 print(" shift", shift.value)
722 print(" finalmask", bin(finalmask.value))
723 res = selectconcat(zero8,
724 (rpn & ~finalmask) | #
725 (abits & finalmask), #
726 addr[52:64],
727 )
728 return res
729
730
731 class TestRadixMMU(unittest.TestCase):
732
733 def test_genmask(self):
734 shift = SelectableInt(5, 6)
735 mask = genmask(shift, 43)
736 print (" mask", bin(mask.value))
737
738 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
739
740 def test_pt(self):
741 inp = SelectableInt(0x40000000000300ad, 64)
742 exp = SelectableInt(0x30000,64)
743
744 # RTS1 = 0x2
745 # RPDB = 0x300
746 # RTS2 = 0x5
747 # RPDS = 13
748
749 print (" inp", bin(inp.value))
750 print (" exp", bin(exp.value))
751 #print ("result", bin(result.value))
752
753 rtdb = pt_RPDB(inp)
754 print("rtdb",rtdb)
755 self.assertEqual(rtdb.value,0x300,"rtdb should be 0x300")
756
757 result = selectconcat(rtdb,SelectableInt(0,8))
758 print("result",result)
759
760
761 def test_get_pgtable_addr(self):
762
763 mem = None
764 caller = None
765 dut = RADIX(mem, caller)
766
767 mask_size=4
768 pgbase = SelectableInt(0,64)
769 addrsh = SelectableInt(0,16)
770 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
771 print("ret=", ret)
772 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
773
774 def test_walk_tree_1(self):
775
776 # test address as in
777 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
778 testaddr = 0x1000
779 expected = 0x1000
780
781 # starting prtbl
782 prtbl = 0x1000000
783
784 # set up dummy minimal ISACaller
785 spr = {'DSISR': SelectableInt(0, 64),
786 'DAR': SelectableInt(0, 64),
787 'PIDR': SelectableInt(0, 64),
788 'PRTBL': SelectableInt(prtbl, 64)
789 }
790 # set problem state == 0 (other unit tests, set to 1)
791 msr = SelectableInt(0, 64)
792 msr[MSRb.PR] = 0
793 class ISACaller: pass
794 caller = ISACaller()
795 caller.spr = spr
796 caller.msr = msr
797
798 shift = SelectableInt(5, 6)
799 mask = genmask(shift, 43)
800 print (" mask", bin(mask.value))
801
802 mem = Mem(row_bytes=8, initial_mem=testmem)
803 mem = RADIX(mem, caller)
804 # -----------------------------------------------
805 # |/|RTS1|/| RPDB | RTS2 | RPDS |
806 # -----------------------------------------------
807 # |0|1 2|3|4 55|56 58|59 63|
808 data = SelectableInt(0, 64)
809 data[1:3] = 0b01
810 data[56:59] = 0b11
811 data[59:64] = 0b01101 # mask
812 data[55] = 1
813 (rts, mbits, pgbase) = mem._decode_prte(data)
814 print (" rts", bin(rts.value), rts.bits)
815 print (" mbits", bin(mbits.value), mbits.bits)
816 print (" pgbase", hex(pgbase.value), pgbase.bits)
817 addr = SelectableInt(0x1000, 64)
818 check = mem._segment_check(addr, mbits, shift)
819 print (" segment check", check)
820
821 print("walking tree")
822 addr = SelectableInt(testaddr,64)
823 # pgbase = None
824 mode = None
825 #mbits = None
826 shift = rts
827 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
828 print(" walking tree result", result)
829 print("should be", testresult)
830 self.assertEqual(result.value, expected,
831 "expected 0x%x got 0x%x" % (expected,
832 result.value))
833
834
835 def test_walk_tree_2(self):
836
837 # test address slightly different
838 testaddr = 0x1101
839 expected = 0x5001101
840
841 # starting prtbl
842 prtbl = 0x1000000
843
844 # set up dummy minimal ISACaller
845 spr = {'DSISR': SelectableInt(0, 64),
846 'DAR': SelectableInt(0, 64),
847 'PIDR': SelectableInt(0, 64),
848 'PRTBL': SelectableInt(prtbl, 64)
849 }
850 # set problem state == 0 (other unit tests, set to 1)
851 msr = SelectableInt(0, 64)
852 msr[MSRb.PR] = 0
853 class ISACaller: pass
854 caller = ISACaller()
855 caller.spr = spr
856 caller.msr = msr
857
858 shift = SelectableInt(5, 6)
859 mask = genmask(shift, 43)
860 print (" mask", bin(mask.value))
861
862 mem = Mem(row_bytes=8, initial_mem=testmem2)
863 mem = RADIX(mem, caller)
864 # -----------------------------------------------
865 # |/|RTS1|/| RPDB | RTS2 | RPDS |
866 # -----------------------------------------------
867 # |0|1 2|3|4 55|56 58|59 63|
868 data = SelectableInt(0, 64)
869 data[1:3] = 0b01
870 data[56:59] = 0b11
871 data[59:64] = 0b01101 # mask
872 data[55] = 1
873 (rts, mbits, pgbase) = mem._decode_prte(data)
874 print (" rts", bin(rts.value), rts.bits)
875 print (" mbits", bin(mbits.value), mbits.bits)
876 print (" pgbase", hex(pgbase.value), pgbase.bits)
877 addr = SelectableInt(0x1000, 64)
878 check = mem._segment_check(addr, mbits, shift)
879 print (" segment check", check)
880
881 print("walking tree")
882 addr = SelectableInt(testaddr,64)
883 # pgbase = None
884 mode = None
885 #mbits = None
886 shift = rts
887 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
888 print(" walking tree result", result)
889 print("should be", testresult)
890 self.assertEqual(result.value, expected,
891 "expected 0x%x got 0x%x" % (expected,
892 result.value))
893
894
895 if __name__ == '__main__':
896 unittest.main()