src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_sv_load_store(self):
  25         lst = SVP64Asm(["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x0008",
  27                         "addi 5, 0, 0x1234",
  28                         "addi 6, 0, 0x1235",
  29                         "sv.stw 5, 0(1)",
  30                         "sv.lwz 9, 0(1)"])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=2)
  34         svstate = SVP64State()
  35         svstate.vl[0:7] = 2 # VL
  36         svstate.maxvl[0:7] = 2 # MAXVL
  37         print ("SVSTATE", bin(svstate.spr.asint()))
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, svstate=svstate)
  41             print(sim.gpr(1))
  42             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  43             #self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  44
  45     def test_sv_add(self):
  46         # adds:
  47         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  48         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  49         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  50                        ])
  51         lst = list(isa)
  52         print ("listing", lst)
  53
  54         # initial values in GPR regfile
  55         initial_regs = [0] * 32
  56         initial_regs[9] = 0x1234
  57         initial_regs[10] = 0x1111
  58         initial_regs[5] = 0x4321
  59         initial_regs[6] = 0x2223
  60         # SVSTATE (in this case, VL=2)
  61         svstate = SVP64State()
  62         svstate.vl[0:7] = 2 # VL
  63         svstate.maxvl[0:7] = 2 # MAXVL
  64         print ("SVSTATE", bin(svstate.spr.asint()))
  65         # copy before running
  66         expected_regs = deepcopy(initial_regs)
  67         expected_regs[1] = 0x5555
  68         expected_regs[2] = 0x3334
  69
  70         with Program(lst, bigendian=False) as program:
  71             sim = self.run_tst_program(program, initial_regs, svstate)
  72             self._check_regs(sim, expected_regs)
  73
  74     def test_sv_add_2(self):
  75         # adds:
  76         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  77         #       r1 is scalar so ENDS EARLY
  78         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  79                        ])
  80         lst = list(isa)
  81         print ("listing", lst)
  82
  83         # initial values in GPR regfile
  84         initial_regs = [0] * 32
  85         initial_regs[9] = 0x1234
  86         initial_regs[10] = 0x1111
  87         initial_regs[5] = 0x4321
  88         initial_regs[6] = 0x2223
  89         # SVSTATE (in this case, VL=2)
  90         svstate = SVP64State()
  91         svstate.vl[0:7] = 2 # VL
  92         svstate.maxvl[0:7] = 2 # MAXVL
  93         print ("SVSTATE", bin(svstate.spr.asint()))
  94         # copy before running
  95         expected_regs = deepcopy(initial_regs)
  96         expected_regs[1] = 0x5555
  97
  98         with Program(lst, bigendian=False) as program:
  99             sim = self.run_tst_program(program, initial_regs, svstate)
 100             self._check_regs(sim, expected_regs)
 101
 102     def test_sv_add_3(self):
 103         # adds:
 104         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 105         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 106         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
 107                        ])
 108         lst = list(isa)
 109         print ("listing", lst)
 110
 111         # initial values in GPR regfile
 112         initial_regs = [0] * 32
 113         initial_regs[9] = 0x1234
 114         initial_regs[10] = 0x1111
 115         initial_regs[5] = 0x4321
 116         initial_regs[6] = 0x2223
 117         # SVSTATE (in this case, VL=2)
 118         svstate = SVP64State()
 119         svstate.vl[0:7] = 2 # VL
 120         svstate.maxvl[0:7] = 2 # MAXVL
 121         print ("SVSTATE", bin(svstate.spr.asint()))
 122         # copy before running
 123         expected_regs = deepcopy(initial_regs)
 124         expected_regs[1] = 0x5555
 125         expected_regs[2] = 0x5432
 126
 127         with Program(lst, bigendian=False) as program:
 128             sim = self.run_tst_program(program, initial_regs, svstate)
 129             self._check_regs(sim, expected_regs)
 130
 131     def test_sv_add_vl_0(self):
 132         # adds:
 133         #       none because VL is zer0
 134         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
 135                        ])
 136         lst = list(isa)
 137         print ("listing", lst)
 138
 139         # initial values in GPR regfile
 140         initial_regs = [0] * 32
 141         initial_regs[9] = 0x1234
 142         initial_regs[10] = 0x1111
 143         initial_regs[5] = 0x4321
 144         initial_regs[6] = 0x2223
 145         # SVSTATE (in this case, VL=0)
 146         svstate = SVP64State()
 147         svstate.vl[0:7] = 0 # VL
 148         svstate.maxvl[0:7] = 0 # MAXVL
 149         print ("SVSTATE", bin(svstate.spr.asint()))
 150         # copy before running
 151         expected_regs = deepcopy(initial_regs)
 152
 153         with Program(lst, bigendian=False) as program:
 154             sim = self.run_tst_program(program, initial_regs, svstate)
 155             self._check_regs(sim, expected_regs)
 156
 157     def test_sv_add_cr(self):
 158         # adds when Rc=1:                               TODO CRs higher up
 159         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 160         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 161         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
 162                        ])
 163         lst = list(isa)
 164         print ("listing", lst)
 165
 166         # initial values in GPR regfile
 167         initial_regs = [0] * 32
 168         initial_regs[9] = 0xffffffffffffffff
 169         initial_regs[10] = 0x1111
 170         initial_regs[5] = 0x1
 171         initial_regs[6] = 0x2223
 172         # SVSTATE (in this case, VL=2)
 173         svstate = SVP64State()
 174         svstate.vl[0:7] = 2 # VL
 175         svstate.maxvl[0:7] = 2 # MAXVL
 176         print ("SVSTATE", bin(svstate.spr.asint()))
 177         # copy before running
 178         expected_regs = deepcopy(initial_regs)
 179         expected_regs[1] = 0
 180         expected_regs[2] = 0x3334
 181
 182         with Program(lst, bigendian=False) as program:
 183             sim = self.run_tst_program(program, initial_regs, svstate)
 184             # XXX TODO, these need to move to higher range (offset)
 185             cr0_idx = SVP64CROffs.CR0
 186             cr1_idx = SVP64CROffs.CR1
 187             CR0 = sim.crl[cr0_idx].get_range().value
 188             CR1 = sim.crl[cr1_idx].get_range().value
 189             print ("CR0", CR0)
 190             print ("CR1", CR1)
 191             self._check_regs(sim, expected_regs)
 192             self.assertEqual(CR0, SelectableInt(2, 4))
 193             self.assertEqual(CR1, SelectableInt(4, 4))
 194
 195     def run_tst_program(self, prog, initial_regs=None,
 196                               svstate=None):
 197         if initial_regs is None:
 198             initial_regs = [0] * 32
 199         simulator = run_tst(prog, initial_regs, svstate=svstate)
 200         simulator.gpr.dump()
 201         return simulator
 202
 203
 204 if __name__ == "__main__":
 205     unittest.main()