src/soc/decoder/power_fieldsn.py

   1 from collections import OrderedDict
   2 from soc.decoder.power_fields import DecodeFields, BitRange
   3 from nmigen import Module, Elaboratable, Signal, Cat
   4 from nmigen.cli import rtlil
   5
   6
   7 class SignalBitRange(BitRange):
   8     def __init__(self, signal):
   9         BitRange.__init__(self)
  10         self.signal = signal
  11
  12     def _rev(self, k):
  13         width = self.signal.shape()[0]
  14         return width-1-k
  15
  16     def __getitem__(self, subs):
  17         # *sigh* field numberings are bit-inverted.  PowerISA 3.0B section 1.3.2
  18         print ("SignalBitRange", subs, len(self), self.items())
  19         if isinstance(subs, slice):
  20             res = []
  21             print (subs)
  22             start, stop, step = subs.start, subs.stop, subs.step
  23             if step is None:
  24                 step = 1
  25             if start is None:
  26                 start = 0
  27             if stop is None:
  28                 stop = -1
  29             if start < 0:
  30                 start = len(self) + start + 1
  31             if stop < 0:
  32                 stop = len(self) + stop + 1
  33             print ("range", start, stop, step)
  34             for t in range(start, stop, step):
  35                 t = len(self) - 1 - t # invert field back
  36                 k = OrderedDict.__getitem__(self, t)
  37                 print ("t", t, k)
  38                 res.append(self.signal[self._rev(k)]) # reverse-order here
  39             return Cat(*res)
  40         else:
  41             if subs < 0:
  42                 subs = len(self) + subs
  43             subs = len(self) - 1 - subs # invert field back
  44             k = OrderedDict.__getitem__(self, subs)
  45             return self.signal[self._rev(k)] # reverse-order here
  46
  47         print ("translated", subs, translated)
  48
  49
  50 class SigDecode(Elaboratable):
  51
  52     def __init__(self, width):
  53         self.opcode_in = Signal(width, reset_less=False)
  54         self.df = DecodeFields(SignalBitRange, [self.opcode_in])
  55         self.df.create_specs()
  56         self.x_s = Signal(len(self.df.FormX.S), reset_less=True)
  57         self.x_sh = Signal(len(self.df.FormX.SH), reset_less=True)
  58         self.dq_xs_s = Signal(len(self.df.FormDQ.SX_S), reset_less=True)
  59
  60     def elaborate(self, platform):
  61         m = Module()
  62         comb = m.d.comb
  63         comb += self.x_s.eq(self.df.FormX.S[0])
  64         comb += self.x_sh.eq(self.df.FormX.SH[0:-1])
  65         comb += self.dq_xs_s.eq(self.df.FormDQ.SX_S[0:-1])
  66         return m
  67
  68     def ports(self):
  69         return [self.opcode_in, self.x_s, self.x_sh]
  70
  71 def create_sigdecode():
  72     s = SigDecode(32)
  73     return s
  74
  75 if __name__ == '__main__':
  76     sigdecode = create_sigdecode()
  77     vl = rtlil.convert(sigdecode, ports=sigdecode.ports())
  78     with open("decoder.il", "w") as f:
  79         f.write(vl)
  80