1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 Both LD and ST may request that the address be computed from summing
24 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
25 the immediate (from the opcode).
27 Both LD and ST may also request "update" mode (op_is_update) which
28 activates the use of Go_Write[1] to control storage of the EA into
29 a *second* operand in the register file.
31 Thus this module has *TWO* write-requests to the register file and
32 *THREE* read-requests to the register file (not all at the same time!)
33 The regfile port usage is:
45 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
46 is not suited to (nmigen.FSM is clock-driven, and some aspects of
47 the nested FSMs below are *combinatorial*).
49 * One FSM covers Operand collection and communication address-side
50 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
52 * A second FSM activates to cover LD. it activates if op_is_ld is true
54 * A third FSM activates to cover ST. it activates if op_is_st is true
56 * The "overall" (fourth) FSM coordinates the progression and completion
57 of the three other FSMs, firing "WR_RESET" which switches off "busy"
61 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
63 Links including to walk-through videos:
65 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
66 * http://libre-soc.org/openpower/isa/fixedload
67 * http://libre-soc.org/openpower/isa/fixedstore
71 * https://bugs.libre-soc.org/show_bug.cgi?id=302
72 * https://bugs.libre-soc.org/show_bug.cgi?id=216
76 * EA - Effective Address
81 from nmigen
.compat
.sim
import run_simulation
82 from nmigen
.cli
import verilog
, rtlil
83 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
84 from nmigen
.hdl
.rec
import Record
, Layout
86 from nmutil
.latch
import SRLatch
, latchregister
88 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
89 from soc
.experiment
.l0_cache
import PortInterface
90 from soc
.experiment
.testmem
import TestMemory
91 from soc
.fu
.regspec
import RegSpecAPI
93 from soc
.decoder
.power_enums
import InternalOp
, Function
94 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
95 from soc
.decoder
.power_decoder2
import Data
98 class LDSTCompUnitRecord(CompUnitRecord
):
99 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
100 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
101 n_src
=3, n_dst
=2, name
=name
)
103 self
.ad
= go_record(1, name
="ad") # address go in, req out
104 self
.st
= go_record(1, name
="st") # store go in, req out
106 self
.addr_exc_o
= Signal(reset_less
=True) # address exception
108 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
109 self
.st_o
= Signal(reset_less
=True) # operation is a ST
111 # hmm... are these necessary?
112 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
113 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
116 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
117 """LOAD / STORE Computation Unit
122 * :pi: a PortInterface to the memory subsystem (read-write capable)
123 * :rwid: register width
124 * :awid: address width
128 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
132 * :data_o: Dest out (LD) - managed by wr[0] go/req
133 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
134 * :addr_exc_o: Address/Data Exception occurred. LD/ST must terminate
136 TODO: make addr_exc_o a data-type rather than a single-bit signal
142 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
143 * :issue_i: LD/ST is being "issued".
144 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
145 * :go_rd_i: read is being actioned (latches in src regs)
146 * :go_wr_i: write mode (exactly like ALU CompUnit)
147 * :go_ad_i: address is being actioned (triggers actual mem LD)
148 * :go_st_i: store is being actioned (triggers actual mem STORE)
149 * :go_die_i: resets the unit back to "wait for issue"
151 Control Signals (Out)
152 ---------------------
154 * :busy_o: function unit is busy
155 * :rd_rel_o: request src1/src2
156 * :adr_rel_o: request address (from mem)
157 * :sto_rel_o: request store (to mem)
158 * :req_rel_o: request write (result)
159 * :load_mem_o: activate memory LOAD
160 * :stwd_mem_o: activate memory STORE
162 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
163 in a single cycle and the CompUnit set back to doing another op.
164 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
165 depending on whether the operation is a ST or LD.
168 def __init__(self
, pi
=None, rwid
=64, awid
=48, opsubset
=CompLDSTOpSubset
,
170 super().__init
__(rwid
)
173 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
)
174 self
.debugtest
= debugtest
176 # POWER-compliant LD/ST has index and update: *fixed* number of ports
177 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
178 self
.n_dst
= n_dst
= 2 # RA, RT/RS
180 # set up array of src and dest signals
181 for i
in range(n_src
):
182 j
= i
+ 1 # name numbering to match src1/src2
184 setattr(self
, name
, getattr(cu
, name
))
187 for i
in range(n_dst
):
188 j
= i
+ 1 # name numbering to match dest1/2...
189 name
= "dest%d_o" % j
190 setattr(self
, name
, getattr(cu
, name
))
195 self
.rdmaskn
= cu
.rdmaskn
196 self
.wrmask
= cu
.wrmask
201 # HACK: get data width from dest[0]. this is used across the board
202 # (it really shouldn't be)
203 self
.data_wid
= self
.dest
[0].shape()
205 self
.go_rd_i
= self
.rd
.go
# temporary naming
206 self
.go_wr_i
= self
.wr
.go
# temporary naming
207 self
.go_ad_i
= self
.ad
.go
# temp naming: go address in
208 self
.go_st_i
= self
.st
.go
# temp naming: go store in
210 self
.rd_rel_o
= self
.rd
.rel
# temporary naming
211 self
.req_rel_o
= self
.wr
.rel
# temporary naming
212 self
.adr_rel_o
= self
.ad
.rel
# request address (from mem)
213 self
.sto_rel_o
= self
.st
.rel
# request store (to mem)
215 self
.issue_i
= cu
.issue_i
216 self
.shadown_i
= cu
.shadown_i
217 self
.go_die_i
= cu
.go_die_i
219 self
.oper_i
= cu
.oper_i
220 self
.src_i
= cu
._src
_i
222 self
.data_o
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
223 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
224 self
.addr_exc_o
= cu
.addr_exc_o
225 self
.done_o
= cu
.done_o
226 self
.busy_o
= cu
.busy_o
231 self
.load_mem_o
= cu
.load_mem_o
232 self
.stwd_mem_o
= cu
.stwd_mem_o
234 def elaborate(self
, platform
):
240 issue_i
= self
.issue_i
242 #####################
243 # latches for the FSM.
244 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
245 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
246 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
247 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
248 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
249 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
250 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
251 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
252 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
258 op_is_ld
= Signal(reset_less
=True)
259 op_is_st
= Signal(reset_less
=True)
261 # ALU/LD data output control
262 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
263 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
264 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
265 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
266 wr_any
= Signal(reset_less
=True) # any write (incl. store)
267 rda_any
= Signal(reset_less
=True) # any read for address ops
268 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
269 wr_reset
= Signal(reset_less
=True) # final reset condition
272 alu_o
= Signal(self
.data_wid
, reset_less
=True)
273 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
275 ##############################
276 # reset conditions for latches
278 # temporaries (also convenient when debugging)
279 reset_o
= Signal(reset_less
=True) # reset opcode
280 reset_w
= Signal(reset_less
=True) # reset write
281 reset_u
= Signal(reset_less
=True) # reset update
282 reset_a
= Signal(reset_less
=True) # reset adr latch
283 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
284 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
285 reset_s
= Signal(reset_less
=True) # reset store
287 comb
+= reset_i
.eq(issue_i | self
.go_die_i
) # various
288 comb
+= reset_o
.eq(wr_reset | self
.go_die_i
) # opcode reset
289 comb
+= reset_w
.eq(self
.wr
.go
[0] | self
.go_die_i
) # write reg 1
290 comb
+= reset_u
.eq(self
.wr
.go
[1] | self
.go_die_i
) # update (reg 2)
291 comb
+= reset_s
.eq(self
.go_st_i | self
.go_die_i
) # store reset
292 comb
+= reset_r
.eq(self
.rd
.go |
Repl(self
.go_die_i
, self
.n_src
))
293 comb
+= reset_a
.eq(self
.go_ad_i | self
.go_die_i
)
295 ##########################
296 # FSM implemented through sequence of latches. approximately this:
298 # - src_l[0] : operands
300 # - alu_l : looks after add of src1/2/imm (EA)
301 # - adr_l : waits for add (EA)
302 # - upd_l : waits for adr and Regfile (port 2)
304 # - lod_l : waits for adr (EA) and for LD Data
305 # - wri_l : waits for LD Data and Regfile (port 1)
306 # - st_l : waits for alu and operand2
307 # - rst_l : waits for all FSM paths to converge.
308 # NOTE: use sync to stop combinatorial loops.
310 # opcode latch - inverted so that busy resets to 0
311 # note this MUST be sync so as to avoid a combinatorial loop
312 # between busy_o and issue_i on the reset latch (rst_l)
313 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
314 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
317 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
))
318 sync
+= src_l
.r
.eq(reset_r
)
320 # alu latch. use sync-delay between alu_ok and valid to generate pulse
321 comb
+= alu_l
.s
.eq(reset_i
)
322 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
325 comb
+= adr_l
.s
.eq(reset_i
)
326 sync
+= adr_l
.r
.eq(reset_a
)
329 comb
+= lod_l
.s
.eq(reset_i
)
330 comb
+= lod_l
.r
.eq(ld_ok
)
333 comb
+= wri_l
.s
.eq(issue_i
)
334 sync
+= wri_l
.r
.eq(reset_w
)
336 # update-mode operand latch (EA written to reg 2)
337 sync
+= upd_l
.s
.eq(reset_i
)
338 sync
+= upd_l
.r
.eq(reset_u
)
341 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st
)
342 comb
+= sto_l
.r
.eq(reset_s
)
345 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
346 comb
+= rst_l
.r
.eq(issue_i
)
348 # create a latch/register for the operand
349 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
350 latchregister(m
, self
.oper_i
, oper_r
, self
.issue_i
, name
="oper_l")
353 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
354 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
356 # and for each input from the incoming src operands
358 for i
in range(self
.n_src
):
360 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
361 latchregister(m
, self
.src_i
[i
], src_r
, src_l
.q
[i
], name
+ '_l')
364 # and one for the output from the ADD (for the EA)
365 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
366 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
368 # select either zero or src1 if opcode says so
369 op_is_z
= oper_r
.zero_a
370 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
371 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
373 # select either immediate or src2 if opcode says so
374 op_is_imm
= oper_r
.imm_data
.imm_ok
375 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
376 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.imm
, srl
[1]))
378 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
379 sync
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
380 sync
+= alu_ok
.eq(alu_valid
) # keep ack in sync with EA
382 # decode bits of operand (latched)
383 comb
+= op_is_st
.eq(oper_r
.insn_type
== InternalOp
.OP_STORE
) # ST
384 comb
+= op_is_ld
.eq(oper_r
.insn_type
== InternalOp
.OP_LOAD
) # LD
385 op_is_update
= oper_r
.update
# UPDATE
386 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
387 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
388 comb
+= self
.ld_o
.eq(op_is_ld
)
389 comb
+= self
.st_o
.eq(op_is_st
)
391 ############################
392 # Control Signal calculation
396 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
398 # 1st operand read-request only when zero not active
399 # 2nd operand only needed when immediate is not active
400 slg
= Cat(op_is_z
, op_is_imm
)
401 bro
= Repl(self
.busy_o
, self
.n_src
)
402 comb
+= self
.rd
.rel
.eq(src_l
.q
& bro
& ~slg
& ~self
.rdmaskn
)
404 # note when the address-related read "go" signals are active
405 comb
+= rda_any
.eq(self
.rd
.go
[0] | self
.rd
.go
[1])
407 # alu input valid when 1st and 2nd ops done (or imm not active)
408 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel
[0] | self
.rd
.rel
[1]))
410 # 3rd operand only needed when operation is a store
411 comb
+= self
.rd
.rel
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
413 # all reads done when alu is valid and 3rd operand needed
414 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel
[2])
416 # address release only if addr ready, but Port must be idle
417 comb
+= self
.adr_rel_o
.eq(adr_l
.q
& busy_o
)
419 # store release when st ready *and* all operands read (and no shadow)
420 comb
+= self
.st
.rel
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st
&
423 # request write of LD result. waits until shadow is dropped.
424 comb
+= self
.wr
.rel
[0].eq(wri_l
.q
& busy_o
& lod_l
.qn
& op_is_ld
&
427 # request write of EA result only in update mode
428 comb
+= self
.wr
.rel
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
431 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
432 comb
+= wr_any
.eq(self
.st
.go | self
.wr
.go
[0] | self
.wr
.go
[1])
433 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& self
.shadown_i
&
434 ~
(self
.st
.rel | self
.wr
.rel
[0] | self
.wr
.rel
[1]) &
435 (lod_l
.qn | op_is_st
))
436 comb
+= self
.done_o
.eq(wr_reset
)
438 ######################
439 # Data/Address outputs
441 # put the LD-output register directly onto the output bus on a go_write
442 comb
+= self
.data_o
.data
.eq(self
.dest
[0])
443 with m
.If(self
.wr
.go
[0]):
444 comb
+= self
.dest
[0].eq(ldd_r
)
446 # "update" mode, put address out on 2nd go-write
447 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
448 with m
.If(op_is_update
& self
.wr
.go
[1]):
449 comb
+= self
.dest
[1].eq(addr_r
)
451 # need to look like MultiCompUnit: put wrmask out.
452 # XXX may need to make this enable only when write active
453 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
455 ###########################
456 # PortInterface connections
459 # connect to LD/ST PortInterface.
460 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
461 comb
+= pi
.is_st_i
.eq(op_is_st
& busy_o
) # decoded-ST
462 comb
+= pi
.op
.eq(self
.oper_i
) # op details (not all needed)
464 comb
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
465 comb
+= pi
.addr
.ok
.eq(alu_ok
& lod_l
.q
) # "go do address stuff"
466 comb
+= self
.addr_exc_o
.eq(pi
.addr_exc_o
) # exception occurred
467 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
468 # ld - ld gets latched in via lod_l
469 comb
+= ldd_o
.eq(pi
.ld
.data
) # ld data goes into ld reg (above)
470 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
471 # store - data goes in based on go_st
472 comb
+= pi
.st
.data
.eq(srl
[2]) # 3rd operand latch
473 comb
+= pi
.st
.ok
.eq(self
.st
.go
) # go store signals st data valid
477 def get_out(self
, i
):
478 """make LDSTCompUnit look like RegSpecALUAPI"""
493 yield from self
.oper_i
.ports()
494 yield from self
.src_i
500 yield from self
.data_o
.ports()
501 yield from self
.addr_o
.ports()
502 yield self
.load_mem_o
503 yield self
.stwd_mem_o
509 def wait_for(sig
, wait
=True, test1st
=False):
511 print("wait for", sig
, v
, wait
, test1st
)
512 if test1st
and bool(v
) == wait
:
517 #print("...wait for", sig, v)
522 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False):
523 print ("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
524 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_STORE
)
525 yield dut
.src1_i
.eq(src1
)
526 yield dut
.src2_i
.eq(src2
)
527 yield dut
.src3_i
.eq(src3
)
528 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
529 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
530 yield dut
.oper_i
.update
.eq(update
)
531 yield dut
.issue_i
.eq(1)
533 yield dut
.issue_i
.eq(0)
536 yield dut
.rd
.go
.eq(0b101)
538 yield dut
.rd
.go
.eq(0b111)
539 yield from wait_for(dut
.rd
.rel
)
540 yield dut
.rd
.go
.eq(0)
542 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
543 #yield from wait_for(dut.adr_rel_o)
544 #yield dut.ad.go.eq(1)
546 #yield dut.ad.go.eq(0)
549 yield from wait_for(dut
.wr
.rel
[1])
550 yield dut
.wr
.go
.eq(0b10)
552 addr
= yield dut
.addr_o
554 yield dut
.wr
.go
.eq(0)
558 yield from wait_for(dut
.sto_rel_o
)
559 yield dut
.go_st_i
.eq(1)
561 yield dut
.go_st_i
.eq(0)
562 yield from wait_for(dut
.busy_o
, False)
563 #wait_for(dut.stwd_mem_o)
568 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False):
569 print ("LD", src1
, src2
, imm
, imm_ok
, update
)
570 yield dut
.oper_i
.insn_type
.eq(InternalOp
.OP_LOAD
)
571 yield dut
.src1_i
.eq(src1
)
572 yield dut
.src2_i
.eq(src2
)
573 yield dut
.oper_i
.zero_a
.eq(zero_a
)
574 yield dut
.oper_i
.imm_data
.imm
.eq(imm
)
575 yield dut
.oper_i
.imm_data
.imm_ok
.eq(imm_ok
)
576 yield dut
.issue_i
.eq(1)
578 yield dut
.issue_i
.eq(0)
587 yield dut
.rd
.go
.eq(rd
)
588 yield from wait_for(dut
.rd
.rel
)
589 yield dut
.rd
.go
.eq(0)
591 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
592 #yield dut.ad.go.eq(1)
594 #yield dut.ad.go.eq(0)
597 yield from wait_for(dut
.wr
.rel
[1])
598 yield dut
.wr
.go
.eq(0b10)
600 addr
= yield dut
.addr_o
602 yield dut
.wr
.go
.eq(0)
606 yield from wait_for(dut
.wr
.rel
[0], test1st
=True)
607 yield dut
.wr
.go
.eq(1)
609 data
= yield dut
.data_o
611 yield dut
.wr
.go
.eq(0)
612 yield from wait_for(dut
.busy_o
)
614 # wait_for(dut.stwd_mem_o)
618 def scoreboard_sim(dut
):
623 # two STs (different addresses)
624 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
625 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
627 # two LDs (deliberately LD from the 1st address then 2nd)
628 data
, addr
= yield from load(dut
, 4, 0, 2)
629 assert data
== 0x0003, "returned %x" % data
630 data
, addr
= yield from load(dut
, 2, 0, 2)
631 assert data
== 0x0009, "returned %x" % data
635 yield from store(dut
, 4, 5, 3, 0, imm_ok
=False)
636 data
, addr
= yield from load(dut
, 4, 5, 0, imm_ok
=False)
637 assert data
== 0x0003, "returned %x" % data
639 # update-immediate version
640 addr
= yield from store(dut
, 4, 6, 3, 2, update
=True)
641 assert addr
== 0x0006, "returned %x" % addr
643 # update-indexed version
644 data
, addr
= yield from load(dut
, 4, 5, 0, imm_ok
=False, update
=True)
645 assert data
== 0x0003, "returned %x" % data
646 assert addr
== 0x0009, "returned %x" % addr
648 # immediate *and* zero version
649 data
, addr
= yield from load(dut
, 4, 5, 9, imm_ok
=True, zero_a
=True)
650 assert data
== 0x0003, "returned %x" % data
653 class TestLDSTCompUnit(LDSTCompUnit
):
655 def __init__(self
, rwid
):
656 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
657 self
.l0
= l0
= TstL0CacheBuffer()
658 pi
= l0
.l0
.dports
[0].pi
659 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
661 def elaborate(self
, platform
):
662 m
= LDSTCompUnit
.elaborate(self
, platform
)
663 m
.submodules
.l0
= self
.l0
664 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
668 def test_scoreboard():
670 dut
= TestLDSTCompUnit(16)
671 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
672 with
open("test_ldst_comp.il", "w") as f
:
675 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_ldst_comp.vcd')
678 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
681 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
682 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
683 regspec
= LDSTPipeSpec
.regspec
684 self
.l0
= l0
= TstL0CacheBuffer()
685 pi
= l0
.l0
.dports
[0].pi
686 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
688 def elaborate(self
, platform
):
689 m
= LDSTCompUnit
.elaborate(self
, platform
)
690 m
.submodules
.l0
= self
.l0
691 m
.d
.comb
+= self
.ad
.go
.eq(self
.ad
.rel
) # link addr-go direct to rel
695 def test_scoreboard_regspec():
697 dut
= TestLDSTCompUnitRegSpec()
698 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
699 with
open("test_ldst_comp.il", "w") as f
:
702 run_simulation(dut
, scoreboard_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
705 if __name__
== '__main__':
706 test_scoreboard_regspec()