3 based on Anton Blanchard microwatt dcache.vhdl
7 from enum
import Enum
, unique
9 from nmigen
import Module
, Signal
, Elaboratable
,
11 from nmigen
.cli
import main
12 from nmigen
.iocontrol
import RecordObject
13 from nmigen
.util
import log2_int
15 from experiment
.mem_types
import LoadStore1ToDcacheType
,
16 DcacheToLoadStore1Type
,
20 from experiment
.wb_types
import WB_ADDR_BITS
, WB_DATA_BITS
, WB_SEL_BITS
,
21 WBAddrType
, WBDataType
, WBSelType
,
22 WbMasterOut
, WBSlaveOut
, WBMasterOutVector
,
23 WBSlaveOutVector
, WBIOMasterOut
,
27 # -- Set associative dcache write-through
29 # -- TODO (in no specific order):
31 # -- * See list in icache.vhdl
32 # -- * Complete load misses on the cycle when WB data comes instead of
33 # -- at the end of line (this requires dealing with requests coming in
34 # -- while not idle...)
37 # use ieee.std_logic_1164.all;
38 # use ieee.numeric_std.all;
42 # use work.common.all;
43 # use work.helpers.all;
44 # use work.wishbone_types.all;
47 class Dcache(Elaboratable
):
49 # -- Line size in bytes
50 # LINE_SIZE : positive := 64;
51 # -- Number of lines in a set
52 # NUM_LINES : positive := 32;
54 # NUM_WAYS : positive := 4;
55 # -- L1 DTLB entries per set
56 # TLB_SET_SIZE : positive := 64;
57 # -- L1 DTLB number of sets
58 # TLB_NUM_WAYS : positive := 2;
59 # -- L1 DTLB log_2(page_size)
60 # TLB_LG_PGSZ : positive := 12;
61 # -- Non-zero to enable log data collection
62 # LOG_LENGTH : natural := 0
67 # Number of lines in a set
71 # L1 DTLB entries per set
72 self
.TLB_SET_SIZE
= 64
73 # L1 DTLB number of sets
75 # L1 DTLB log_2(page_size)
77 # Non-zero to enable log data collection
80 # clk : in std_ulogic;
81 # rst : in std_ulogic;
83 # d_in : in Loadstore1ToDcacheType;
84 # d_out : out DcacheToLoadstore1Type;
86 # m_in : in MmuToDcacheType;
87 # m_out : out DcacheToMmuType;
89 # stall_out : out std_ulogic;
91 # wishbone_out : out wishbone_master_out;
92 # wishbone_in : in wishbone_slave_out;
94 # log_out : out std_ulogic_vector(19 downto 0)
96 self
.d_in
= LoadStore1ToDcacheType()
97 self
.d_out
= DcacheToLoadStore1Type()
99 self
.m_in
= MmuToDcacheType()
100 self
.m_out
= DcacheToMmuType()
102 self
.stall_out
= Signal()
104 self
.wb_out
= WBMasterOut()
105 self
.wb_in
= WBSlaveOut()
107 self
.log_out
= Signal(20)
110 # architecture rtl of dcache is
111 def elaborate(self
, platform
):
112 LINE_SIZE
= self
.LINE_SIZE
113 NUM_LINES
= self
.NUM_LINES
114 NUM_WAYS
= self
.NUM_WAYS
115 TLB_SET_SIZE
= self
.TLB_SET_SIZE
116 TLB_NUM_WAYS
= self
.TLB_NUM_WAYS
117 TLB_LG_PGSZ
= self
.TLB_LG_PGSZ
118 LOG_LENGTH
= self
.LOG_LENGTH
120 # -- BRAM organisation: We never access more than
121 # -- wishbone_data_bits at a time so to save
122 # -- resources we make the array only that wide, and
123 # -- use consecutive indices for to make a cache "line"
125 # -- ROW_SIZE is the width in bytes of the BRAM
126 # -- (based on WB, so 64-bits)
127 # constant ROW_SIZE : natural := wishbone_data_bits / 8;
128 # BRAM organisation: We never access more than
129 # -- wishbone_data_bits at a time so to save
130 # -- resources we make the array only that wide, and
131 # -- use consecutive indices for to make a cache "line"
133 # -- ROW_SIZE is the width in bytes of the BRAM
134 # -- (based on WB, so 64-bits)
135 ROW_SIZE
= wishbone_data_bits
/ 8;
137 # -- ROW_PER_LINE is the number of row (wishbone
138 # -- transactions) in a line
139 # constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
140 # -- BRAM_ROWS is the number of rows in BRAM needed
141 # -- to represent the full dcache
142 # constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
143 # ROW_PER_LINE is the number of row (wishbone
144 # transactions) in a line
145 ROW_PER_LINE
= LINE_SIZE
/ ROW_SIZE
146 # BRAM_ROWS is the number of rows in BRAM needed
147 # to represent the full dcache
148 BRAM_ROWS
= NUM_LINES
* ROW_PER_LINE
150 # -- Bit fields counts in the address
152 # -- REAL_ADDR_BITS is the number of real address
153 # -- bits that we store
154 # constant REAL_ADDR_BITS : positive := 56;
155 # -- ROW_BITS is the number of bits to select a row
156 # constant ROW_BITS : natural := log2(BRAM_ROWS);
157 # -- ROW_LINEBITS is the number of bits to select
158 # -- a row within a line
159 # constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
160 # -- LINE_OFF_BITS is the number of bits for
161 # -- the offset in a cache line
162 # constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
163 # -- ROW_OFF_BITS is the number of bits for
164 # -- the offset in a row
165 # constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
166 # -- INDEX_BITS is the number if bits to
167 # -- select a cache line
168 # constant INDEX_BITS : natural := log2(NUM_LINES);
169 # -- SET_SIZE_BITS is the log base 2 of the set size
170 # constant SET_SIZE_BITS : natural := LINE_OFF_BITS
172 # -- TAG_BITS is the number of bits of
173 # -- the tag part of the address
174 # constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
175 # -- TAG_WIDTH is the width in bits of each way of the tag RAM
176 # constant TAG_WIDTH : natural := TAG_BITS + 7
177 # - ((TAG_BITS + 7) mod 8);
178 # -- WAY_BITS is the number of bits to select a way
179 # constant WAY_BITS : natural := log2(NUM_WAYS);
180 # Bit fields counts in the address
182 # REAL_ADDR_BITS is the number of real address
185 # ROW_BITS is the number of bits to select a row
186 ROW_BITS
= log2_int(BRAM_ROWS
)
187 # ROW_LINE_BITS is the number of bits to select
188 # a row within a line
189 ROW_LINE_BITS
= log2_int(ROW_PER_LINE
)
190 # LINE_OFF_BITS is the number of bits for
191 # the offset in a cache line
192 LINE_OFF_BITS
= log2_int(LINE_SIZE
)
193 # ROW_OFF_BITS is the number of bits for
194 # the offset in a row
195 ROW_OFF_BITS
= log2_int(ROW_SIZE
)
196 # INDEX_BITS is the number if bits to
197 # select a cache line
198 INDEX_BITS
= log2_int(NUM_LINES
)
199 # SET_SIZE_BITS is the log base 2 of the set size
200 SET_SIZE_BITS
= LINE_OFF_BITS
+ INDEX_BITS
201 # TAG_BITS is the number of bits of
202 # the tag part of the address
203 TAG_BITS
= REAL_ADDR_BITS
- SET_SIZE_BITS
204 # TAG_WIDTH is the width in bits of each way of the tag RAM
205 TAG_WIDTH
= TAG_BITS
+ 7 - ((TAG_BITS
+ 7) % 8)
206 # WAY_BITS is the number of bits to select a way
207 WAY_BITS
= log2_int(NUM_WAYS
)
209 # -- Example of layout for 32 lines of 64 bytes:
211 # -- .. tag |index| line |
213 # -- .. | |---| | ROW_LINEBITS (3)
214 # -- .. | |--- - --| LINE_OFF_BITS (6)
215 # -- .. | |- --| ROW_OFF_BITS (3)
216 # -- .. |----- ---| | ROW_BITS (8)
217 # -- .. |-----| | INDEX_BITS (5)
218 # -- .. --------| | TAG_BITS (45)
219 # Example of layout for 32 lines of 64 bytes:
221 # .. tag |index| line |
223 # .. | |---| | ROW_LINE_BITS (3)
224 # .. | |--- - --| LINE_OFF_BITS (6)
225 # .. | |- --| ROW_OFF_BITS (3)
226 # .. |----- ---| | ROW_BITS (8)
227 # .. |-----| | INDEX_BITS (5)
228 # .. --------| | TAG_BITS (45)
231 # subtype row_t is integer range 0 to BRAM_ROWS-1;
232 # subtype index_t is integer range 0 to NUM_LINES-1;
233 # subtype way_t is integer range 0 to NUM_WAYS-1;
234 # subtype row_in_line_t is unsigned(ROW_LINE_BITS-1 downto 0);
236 return Signal(BRAM_ROWS
)
239 return Signal(NUM_LINES
)
242 return Signal(NUM_WAYS
)
245 return Signal(ROW_LINE_BITS
)
247 # -- The cache data BRAM organized as described above for each way
248 # subtype cache_row_t is
249 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
250 # The cache data BRAM organized as described above for each way
252 return Signal(WB_DATA_BITS
)
254 # -- The cache tags LUTRAM has a row per set.
255 # -- Vivado is a pain and will not handle a
256 # -- clean (commented) definition of the cache
257 # -- tags as a 3d memory. For now, work around
258 # -- it by putting all the tags
259 # subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
260 # The cache tags LUTRAM has a row per set.
261 # Vivado is a pain and will not handle a
262 # clean (commented) definition of the cache
263 # tags as a 3d memory. For now, work around
264 # it by putting all the tags
266 return Signal(TAG_BITS
)
268 # -- type cache_tags_set_t is array(way_t) of cache_tag_t;
269 # -- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
270 # constant TAG_RAM_WIDTH : natural := TAG_WIDTH * NUM_WAYS;
271 # subtype cache_tags_set_t is
272 # std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
273 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
274 # type cache_tags_set_t is array(way_t) of cache_tag_t;
275 # type cache_tags_array_t is array(index_t) of cache_tags_set_t;
276 TAG_RAM_WIDTH
= TAG_WIDTH
* NUM_WAYS
279 return Signal(TAG_RAM_WIDTH
)
282 return Array(CacheTagSet() for x
in range(Index()))
284 # -- The cache valid bits
285 # subtype cache_way_valids_t is
286 # std_ulogic_vector(NUM_WAYS-1 downto 0);
287 # type cache_valids_t is array(index_t) of cache_way_valids_t;
288 # type row_per_line_valid_t is
289 # array(0 to ROW_PER_LINE - 1) of std_ulogic;
290 # The cache valid bits
291 def CacheWayValidBits():
292 return Signal(NUM_WAYS
)
293 def CacheValidBits():
294 return Array(CacheWayValidBits() for x
in range(Index()))
295 def RowPerLineValid():
296 return Array(Signal() for x
in range(ROW_PER_LINE
))
298 # -- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
299 # signal cache_tags : cache_tags_array_t;
300 # signal cache_tag_set : cache_tags_set_t;
301 # signal cache_valids : cache_valids_t;
303 # attribute ram_style : string;
304 # attribute ram_style of cache_tags : signal is "distributed";
305 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
306 cache_tags
= CacheTagArray()
307 cache_tag_set
= CacheTagSet()
308 cache_valid_bits
= CacheValidBits()
310 # TODO attribute ram_style : string;
311 # TODO attribute ram_style of cache_tags : signal is "distributed";
314 # constant TLB_SET_BITS : natural := log2(TLB_SET_SIZE);
315 # constant TLB_WAY_BITS : natural := log2(TLB_NUM_WAYS);
316 # constant TLB_EA_TAG_BITS : natural :=
317 # 64 - (TLB_LG_PGSZ + TLB_SET_BITS);
318 # constant TLB_TAG_WAY_BITS : natural :=
319 # TLB_NUM_WAYS * TLB_EA_TAG_BITS;
320 # constant TLB_PTE_BITS : natural := 64;
321 # constant TLB_PTE_WAY_BITS : natural :=
322 # TLB_NUM_WAYS * TLB_PTE_BITS;
324 TLB_SET_BITS
= log2_int(TLB_SET_SIZE
)
325 TLB_WAY_BITS
= log2_int(TLB_NUM_WAYS
)
326 TLB_EA_TAG_BITS
= 64 - (TLB_LG_PGSZ
+ TLB_SET_BITS
)
327 TLB_TAG_WAY_BITS
= TLB_NUM_WAYS
* TLB_EA_TAG_BITS
329 TLB_PTE_WAY_BITS
= TLB_NUM_WAYS
* TLB_PTE_BITS
;
331 # subtype tlb_way_t is integer range 0 to TLB_NUM_WAYS - 1;
332 # subtype tlb_index_t is integer range 0 to TLB_SET_SIZE - 1;
333 # subtype tlb_way_valids_t is
334 # std_ulogic_vector(TLB_NUM_WAYS-1 downto 0);
335 # type tlb_valids_t is
336 # array(tlb_index_t) of tlb_way_valids_t;
337 # subtype tlb_tag_t is
338 # std_ulogic_vector(TLB_EA_TAG_BITS - 1 downto 0);
339 # subtype tlb_way_tags_t is
340 # std_ulogic_vector(TLB_TAG_WAY_BITS-1 downto 0);
342 # array(tlb_index_t) of tlb_way_tags_t;
343 # subtype tlb_pte_t is
344 # std_ulogic_vector(TLB_PTE_BITS - 1 downto 0);
345 # subtype tlb_way_ptes_t is
346 # std_ulogic_vector(TLB_PTE_WAY_BITS-1 downto 0);
347 # type tlb_ptes_t is array(tlb_index_t) of tlb_way_ptes_t;
348 # type hit_way_set_t is array(tlb_way_t) of way_t;
350 return Signal(TLB_NUM_WAYS
)
352 def TLBWayValidBits():
353 return Signal(TLB_NUM_WAYS
)
356 return Array(TLBValidBits() for x
in range(TLB_SET_SIZE
))
359 return Signal(TLB_EA_TAG_BITS
)
362 return Signal(TLB_TAG_WAY_BITS
)
365 return Array(TLBWayTags() for x
in range (TLB_SET_SIZE
))
368 return Signal(TLB_PTE_BITS
)
371 return Signal(TLB_PTE_WAY_BITS
)
374 return Array(TLBWayPtes() for x
in range(TLB_SET_SIZE
))
377 return Array(Way() for x
in range(TLB_NUM_WAYS
))
379 # signal dtlb_valids : tlb_valids_t;
380 # signal dtlb_tags : tlb_tags_t;
381 # signal dtlb_ptes : tlb_ptes_t;
383 """note: these are passed to nmigen.hdl.Memory as "attributes". don't
384 know how, just that they are.
386 # attribute ram_style of dtlb_tags : signal is "distributed";
387 # attribute ram_style of dtlb_ptes : signal is "distributed";
388 dtlb_valids
= tlb_valids_t
;
389 dtlb_tags
= tlb_tags_t
;
390 dtlb_ptes
= tlb_ptes_t
;
391 # TODO attribute ram_style of dtlb_tags : signal is "distributed";
392 # TODO attribute ram_style of dtlb_ptes : signal is "distributed";
395 # -- Record for storing permission, attribute, etc. bits from a PTE
396 # type perm_attr_t is record
397 # reference : std_ulogic;
398 # changed : std_ulogic;
399 # nocache : std_ulogic;
401 # rd_perm : std_ulogic;
402 # wr_perm : std_ulogic;
404 # Record for storing permission, attribute, etc. bits from a PTE
405 class PermAttr(RecordObject
):
408 self
.reference
= Signal()
409 self
.changed
= Signal()
410 self
.nocache
= Signal()
412 self
.rd_perm
= Signal()
413 self
.wr_perm
= Signal()
415 # function extract_perm_attr(
416 # pte : std_ulogic_vector(TLB_PTE_BITS - 1 downto 0))
417 # return perm_attr_t is
418 # variable pa : perm_attr_t;
420 # pa.reference := pte(8);
421 # pa.changed := pte(7);
422 # pa.nocache := pte(5);
424 # pa.rd_perm := pte(2);
425 # pa.wr_perm := pte(1);
428 def extract_perm_attr(pte
=Signal(TLB_PTE_BITS
)):
430 pa
.reference
= pte
[8]
438 # constant real_mode_perm_attr : perm_attr_t :=
439 # (nocache => '0', others => '1');
440 REAL_MODE_PERM_ATTR
= PermAttr()
441 REAL_MODE_PERM_ATTR
.reference
= 1
442 REAL_MODE_PERM_ATTR
.changed
= 1
443 REAL_MODE_PERM_ATTR
.priv
= 1
444 REAL_MODE_PERM_ATTR
.rd_perm
= 1
445 REAL_MODE_PERM_ATTR
.wr_perm
= 1
447 # -- Type of operation on a "valid" input
451 # OP_BAD, -- NC cache hit, TLB miss, prot/RC failure
452 # OP_STCX_FAIL, -- conditional store w/o reservation
453 # OP_LOAD_HIT, -- Cache hit on load
454 # OP_LOAD_MISS, -- Load missing cache
455 # OP_LOAD_NC, -- Non-cachable load
456 # OP_STORE_HIT, -- Store hitting cache
457 # OP_STORE_MISS -- Store missing cache
459 # Type of operation on a "valid" input
463 OP_BAD
= 1 # NC cache hit, TLB miss, prot/RC failure
464 OP_STCX_FAIL
= 2 # conditional store w/o reservation
465 OP_LOAD_HIT
= 3 # Cache hit on load
466 OP_LOAD_MISS
= 4 # Load missing cache
467 OP_LOAD_NC
= 5 # Non-cachable load
468 OP_STORE_HIT
= 6 # Store hitting cache
469 OP_STORE_MISS
= 7 # Store missing cache
471 # -- Cache state machine
474 # IDLE, -- Normal load hit processing
475 # RELOAD_WAIT_ACK, -- Cache reload wait ack
476 # STORE_WAIT_ACK, -- Store wait ack
477 # NC_LOAD_WAIT_ACK -- Non-cachable load wait ack
479 # Cache state machine
482 IDLE
= 0 # Normal load hit processing
483 RELOAD_WAIT_ACK
= 1 # Cache reload wait ack
484 STORE_WAIT_ACK
= 2 # Store wait ack
485 NC_LOAD_WAIT_ACK
= 3 # Non-cachable load wait ack
487 # -- Dcache operations:
489 # -- In order to make timing, we use the BRAMs with
490 # -- an output buffer, which means that the BRAM
491 # -- output is delayed by an extra cycle.
493 # -- Thus, the dcache has a 2-stage internal pipeline
494 # -- for cache hits with no stalls.
496 # -- All other operations are handled via stalling
497 # -- in the first stage.
499 # -- The second stage can thus complete a hit at the same
500 # -- time as the first stage emits a stall for a complex op.
502 # -- Stage 0 register, basically contains just the latched request
503 # type reg_stage_0_t is record
504 # req : Loadstore1ToDcacheType;
505 # tlbie : std_ulogic;
506 # doall : std_ulogic;
507 # tlbld : std_ulogic;
508 # mmu_req : std_ulogic; -- indicates source of request
512 # In order to make timing, we use the BRAMs with
513 # an output buffer, which means that the BRAM
514 # output is delayed by an extra cycle.
516 # Thus, the dcache has a 2-stage internal pipeline
517 # for cache hits with no stalls.
519 # All other operations are handled via stalling
520 # in the first stage.
522 # The second stage can thus complete a hit at the same
523 # time as the first stage emits a stall for a complex op.
525 # Stage 0 register, basically contains just the latched request
526 class RegStage0(RecordObject
):
529 self
.req
= LoadStore1ToDcacheType()
530 self
.tlbie
= Signal()
531 self
.doall
= Signal()
532 self
.tlbld
= Signal()
533 self
.mmu_req
= Signal() # indicates source of request
535 # signal r0 : reg_stage_0_t;
536 # signal r0_full : std_ulogic;
540 # type mem_access_request_t is record
542 # valid : std_ulogic;
544 # real_addr : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
545 # data : std_ulogic_vector(63 downto 0);
546 # byte_sel : std_ulogic_vector(7 downto 0);
548 # same_tag : std_ulogic;
549 # mmu_req : std_ulogic;
551 class MemAccessRequest(RecordObject
):
555 self
.valid
= Signal()
557 self
.real_addr
= Signal(REAL_ADDR_BITS
)
558 self
.data
= Signal(64)
559 self
.byte_sel
= Signal(8)
561 self
.same_tag
= Signal()
562 self
.mmu_req
= Signal()
564 # -- First stage register, contains state for stage 1 of load hits
565 # -- and for the state machine used by all other operations
566 # type reg_stage_1_t is record
567 # -- Info about the request
568 # full : std_ulogic; -- have uncompleted request
569 # mmu_req : std_ulogic; -- request is from MMU
570 # req : mem_access_request_t;
574 # hit_load_valid : std_ulogic;
575 # hit_index : index_t;
576 # cache_hit : std_ulogic;
579 # tlb_hit : std_ulogic;
580 # tlb_hit_way : tlb_way_t;
581 # tlb_hit_index : tlb_index_t;
583 # -- 2-stage data buffer for data forwarded from writes to reads
584 # forward_data1 : std_ulogic_vector(63 downto 0);
585 # forward_data2 : std_ulogic_vector(63 downto 0);
586 # forward_sel1 : std_ulogic_vector(7 downto 0);
587 # forward_valid1 : std_ulogic;
588 # forward_way1 : way_t;
589 # forward_row1 : row_t;
590 # use_forward1 : std_ulogic;
591 # forward_sel : std_ulogic_vector(7 downto 0);
593 # -- Cache miss state (reload state machine)
596 # write_bram : std_ulogic;
597 # write_tag : std_ulogic;
598 # slow_valid : std_ulogic;
599 # wb : wishbone_master_out;
600 # reload_tag : cache_tag_t;
603 # store_index : index_t;
604 # end_row_ix : row_in_line_t;
605 # rows_valid : row_per_line_valid_t;
606 # acks_pending : unsigned(2 downto 0);
607 # inc_acks : std_ulogic;
608 # dec_acks : std_ulogic;
610 # -- Signals to complete (possibly with error)
611 # ls_valid : std_ulogic;
612 # ls_error : std_ulogic;
613 # mmu_done : std_ulogic;
614 # mmu_error : std_ulogic;
615 # cache_paradox : std_ulogic;
617 # -- Signal to complete a failed stcx.
618 # stcx_fail : std_ulogic;
620 # First stage register, contains state for stage 1 of load hits
621 # and for the state machine used by all other operations
622 class RegStage1(RecordObject
):
625 # Info about the request
626 self
.full
= Signal() # have uncompleted request
627 self
.mmu_req
= Signal() # request is from MMU
628 self
.req
= MemAccessRequest()
632 self
.hit_load_valid
= Signal()
633 self
.hit_index
= Index()
634 self
.cache_hit
= Signal()
637 self
.tlb_hit
= Signal()
638 self
.tlb_hit_way
= TLBWay()
639 self
.tlb_hit_index
= Signal(TLB_SET_SIZE
)
641 # 2-stage data buffer for data forwarded from writes to reads
642 self
.forward_data1
= Signal(64)
643 self
.forward_data2
= Signal(64)
644 self
.forward_sel1
= Signal(8)
645 self
.forward_valid1
= Signal()
646 self
.forward_way1
= Way()
647 self
.forward_row1
= Row()
648 self
.use_forward1
= Signal()
649 self
.forward_sel
= Signal(8)
651 # Cache miss state (reload state machine)
654 self
.write_bram
= Signal()
655 self
.write_tag
= Signal()
656 self
.slow_valid
= Signal()
657 self
.wb
= WishboneMasterOut()
658 self
.reload_tag
= CacheTag()
659 self
.store_way
= Way()
660 self
.store_row
= Row()
661 self
.store_index
= Index()
662 self
.end_row_ix
= RowInLine()
663 self
.rows_valid
= RowPerLineValid()
664 self
.acks_pending
= Signal(3)
665 self
.inc_acks
= Signal()
666 self
.dec_acks
= Signal()
668 # Signals to complete (possibly with error)
669 self
.ls_valid
= Signal()
670 self
.ls_error
= Signal()
671 self
.mmu_done
= Signal()
672 self
.mmu_error
= Signal()
673 self
.cache_paradox
= Signal()
675 # Signal to complete a failed stcx.
676 self
.stcx_fail
= Signal()
678 # signal r1 : reg_stage_1_t;
681 # -- Reservation information
683 # type reservation_t is record
684 # valid : std_ulogic;
685 # addr : std_ulogic_vector(63 downto LINE_OFF_BITS);
687 # Reservation information
689 class Reservation(RecordObject
):
693 # TODO LINE_OFF_BITS is 6
694 addr
= Signal(63 downto LINE_OFF_BITS
)
696 # signal reservation : reservation_t;
697 reservation
= Reservation()
699 # -- Async signals on incoming request
700 # signal req_index : index_t;
701 # signal req_row : row_t;
702 # signal req_hit_way : way_t;
703 # signal req_tag : cache_tag_t;
704 # signal req_op : op_t;
705 # signal req_data : std_ulogic_vector(63 downto 0);
706 # signal req_same_tag : std_ulogic;
707 # signal req_go : std_ulogic;
708 # Async signals on incoming request
714 req_data
= Signal(64)
715 req_same_tag
= Signal()
718 # signal early_req_row : row_t;
720 # signal cancel_store : std_ulogic;
721 # signal set_rsrv : std_ulogic;
722 # signal clear_rsrv : std_ulogic;
724 # signal r0_valid : std_ulogic;
725 # signal r0_stall : std_ulogic;
727 # signal use_forward1_next : std_ulogic;
728 # signal use_forward2_next : std_ulogic;
729 early_req_row
= Row()
731 cancel_store
= Signal()
733 clear_rsrv
= Signal()
738 use_forward1_next
= Signal()
739 use_forward2_next
= Signal()
741 # -- Cache RAM interface
742 # type cache_ram_out_t is array(way_t) of cache_row_t;
743 # signal cache_out : cache_ram_out_t;
744 # Cache RAM interface
746 return Array(CacheRow() for x
in range(NUM_WAYS
))
748 cache_out
= CacheRamOut()
750 # -- PLRU output interface
751 # type plru_out_t is array(index_t) of
752 # std_ulogic_vector(WAY_BITS-1 downto 0);
753 # signal plru_victim : plru_out_t;
754 # signal replace_way : way_t;
755 # PLRU output interface
757 return Array(Signal(WAY_BITS
) for x
in range(Index()))
759 plru_victim
= PLRUOut()
762 # -- Wishbone read/write/cache write formatting signals
763 # signal bus_sel : std_ulogic_vector(7 downto 0);
764 # Wishbone read/write/cache write formatting signals
768 # signal tlb_tag_way : tlb_way_tags_t;
769 # signal tlb_pte_way : tlb_way_ptes_t;
770 # signal tlb_valid_way : tlb_way_valids_t;
771 # signal tlb_req_index : tlb_index_t;
772 # signal tlb_hit : std_ulogic;
773 # signal tlb_hit_way : tlb_way_t;
774 # signal pte : tlb_pte_t;
775 # signal ra : std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
776 # signal valid_ra : std_ulogic;
777 # signal perm_attr : perm_attr_t;
778 # signal rc_ok : std_ulogic;
779 # signal perm_ok : std_ulogic;
780 # signal access_ok : std_ulogic;
782 tlb_tag_way
= TLBWayTags()
783 tlb_pte_way
= TLBWayPtes()
784 tlb_valid_way
= TLBWayValidBits()
785 tlb_req_index
= Signal(TLB_SET_SIZE
)
787 tlb_hit_way
= TLBWay()
789 ra
= Signal(REAL_ADDR_BITS
)
791 perm_attr
= PermAttr()
796 # -- TLB PLRU output interface
797 # type tlb_plru_out_t is array(tlb_index_t) of
798 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
799 # signal tlb_plru_victim : tlb_plru_out_t;
800 # TLB PLRU output interface
802 return Array(Signal(TLB_WAY_BITS
) for x
in range(TLB_SET_SIZE
))
804 tlb_plru_victim
= TLBPLRUOut()
806 # -- Helper functions to decode incoming requests
808 # -- Return the cache line index (tag index) for an address
809 # function get_index(addr: std_ulogic_vector) return index_t is
812 # unsigned(addr(SET_SIZE_BITS - 1 downto LINE_OFF_BITS))
815 # Helper functions to decode incoming requests
817 # Return the cache line index (tag index) for an address
819 return addr
[LINE_OFF_BITS
:SET_SIZE_BITS
]
821 # -- Return the cache row index (data memory) for an address
822 # function get_row(addr: std_ulogic_vector) return row_t is
825 # unsigned(addr(SET_SIZE_BITS - 1 downto ROW_OFF_BITS))
828 # Return the cache row index (data memory) for an address
830 return addr
[ROW_OFF_BITS
:SET_SIZE_BITS
]
832 # -- Return the index of a row within a line
833 # function get_row_of_line(row: row_t) return row_in_line_t is
834 # variable row_v : unsigned(ROW_BITS-1 downto 0);
836 # row_v := to_unsigned(row, ROW_BITS);
837 # return row_v(ROW_LINEBITS-1 downto 0);
839 # Return the index of a row within a line
840 def get_row_of_line(row
):
841 row_v
= Signal(ROW_BITS
)
843 return row_v
[0:ROW_LINE_BITS
]
845 # -- Returns whether this is the last row of a line
846 # function is_last_row_addr(addr: wishbone_addr_type;
847 # last: row_in_line_t) return boolean is
850 # unsigned(addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS)) = last;
852 # Returns whether this is the last row of a line
853 def is_last_row_addr(addr
, last
):
854 return addr
[ROW_OFF_BITS
:LINE_OFF_BITS
] == last
856 # -- Returns whether this is the last row of a line
857 # function is_last_row(row: row_t; last: row_in_line_t)
860 # return get_row_of_line(row) = last;
862 # Returns whether this is the last row of a line
863 def is_last_row(row
, last
):
864 return get_row_of_line(row
) == last
866 # -- Return the address of the next row in the current cache line
867 # function next_row_addr(addr: wishbone_addr_type)
868 # return std_ulogic_vector is
869 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
870 # variable result : wishbone_addr_type;
872 # -- Is there no simpler way in VHDL to
873 # -- generate that 3 bits adder ?
874 # row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
875 # row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
877 # result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
880 # Return the address of the next row in the current cache line
881 def next_row_addr(addr
):
882 row_idx
= Signal(ROW_LINE_BITS
)
883 result
= WBAddrType()
884 # Is there no simpler way in VHDL to
885 # generate that 3 bits adder ?
886 row_idx
= addr
[ROW_OFF_BITS
:LINE_OFF_BITS
]
887 row_idx
= Signal(row_idx
+ 1)
889 result
[ROW_OFF_BITS
:LINE_OFF_BITS
] = row_idx
892 # -- Return the next row in the current cache line. We use a
893 # -- dedicated function in order to limit the size of the
894 # -- generated adder to be only the bits within a cache line
895 # -- (3 bits with default settings)
896 # function next_row(row: row_t) return row_t is
897 # variable row_v : std_ulogic_vector(ROW_BITS-1 downto 0);
898 # variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
899 # variable result : std_ulogic_vector(ROW_BITS-1 downto 0);
901 # row_v := std_ulogic_vector(to_unsigned(row, ROW_BITS));
902 # row_idx := row_v(ROW_LINEBITS-1 downto 0);
903 # row_v(ROW_LINEBITS-1 downto 0) :=
904 # std_ulogic_vector(unsigned(row_idx) + 1);
905 # return to_integer(unsigned(row_v));
907 # Return the next row in the current cache line. We use a
908 # dedicated function in order to limit the size of the
909 # generated adder to be only the bits within a cache line
910 # (3 bits with default settings)
912 row_v
= Signal(ROW_BITS
)
913 row_idx
= Signal(ROW_LINE_BITS
)
914 result
= Signal(ROW_BITS
)
917 row_idx
= row_v
[ROW_LINE_BITS
]
918 row_v
[0:ROW_LINE_BITS
] = Signal(row_idx
+ 1)
921 # -- Get the tag value from the address
922 # function get_tag(addr: std_ulogic_vector) return cache_tag_t is
924 # return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
926 # Get the tag value from the address
928 return addr
[SET_SIZE_BITS
:REAL_ADDR_BITS
]
930 # -- Read a tag from a tag memory row
931 # function read_tag(way: way_t; tagset: cache_tags_set_t)
932 # return cache_tag_t is
934 # return tagset(way * TAG_WIDTH + TAG_BITS
935 # - 1 downto way * TAG_WIDTH);
937 # Read a tag from a tag memory row
938 def read_tag(way
, tagset
):
939 return tagset
[way
*TAG_WIDTH
:way
* TAG_WIDTH
+ TAG_BITS
]
941 # -- Read a TLB tag from a TLB tag memory row
942 # function read_tlb_tag(way: tlb_way_t; tags: tlb_way_tags_t)
943 # return tlb_tag_t is
944 # variable j : integer;
946 # j := way * TLB_EA_TAG_BITS;
947 # return tags(j + TLB_EA_TAG_BITS - 1 downto j);
949 # Read a TLB tag from a TLB tag memory row
950 def read_tlb_tag(way
, tags
):
953 j
= way
* TLB_EA_TAG_BITS
954 return tags
[j
:j
+ TLB_EA_TAG_BITS
]
956 # -- Write a TLB tag to a TLB tag memory row
957 # procedure write_tlb_tag(way: tlb_way_t; tags: inout tlb_way_tags_t;
959 # variable j : integer;
961 # j := way * TLB_EA_TAG_BITS;
962 # tags(j + TLB_EA_TAG_BITS - 1 downto j) := tag;
964 # Write a TLB tag to a TLB tag memory row
965 def write_tlb_tag(way
, tags
), tag
):
968 j
= way
* TLB_EA_TAG_BITS
969 tags
[j
:j
+ TLB_EA_TAG_BITS
] = tag
971 # -- Read a PTE from a TLB PTE memory row
972 # function read_tlb_pte(way: tlb_way_t; ptes: tlb_way_ptes_t)
973 # return tlb_pte_t is
974 # variable j : integer;
976 # j := way * TLB_PTE_BITS;
977 # return ptes(j + TLB_PTE_BITS - 1 downto j);
979 # Read a PTE from a TLB PTE memory row
980 def read_tlb_pte(way
, ptes
):
983 j
= way
* TLB_PTE_BITS
984 return ptes
[j
:j
+ TLB_PTE_BITS
]
986 # procedure write_tlb_pte(way: tlb_way_t;
987 # ptes: inout tlb_way_ptes_t; newpte: tlb_pte_t) is
988 # variable j : integer;
990 # j := way * TLB_PTE_BITS;
991 # ptes(j + TLB_PTE_BITS - 1 downto j) := newpte;
993 def write_tlb_pte(way
, ptes
),
998 j
= way
* TLB_PTE_BITS
999 return ptes
[j
:j
+ TLB_PTE_BITS
] = newpte
1003 """these, because they are constants, can actually be done *as*
1005 assert LINE_SIZE % ROWSIZE == 0, "line size not ...."
1007 # assert LINE_SIZE mod ROW_SIZE = 0
1008 # report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
1009 # assert ispow2(LINE_SIZE)
1010 # report "LINE_SIZE not power of 2" severity FAILURE;
1011 # assert ispow2(NUM_LINES)
1012 # report "NUM_LINES not power of 2" severity FAILURE;
1013 # assert ispow2(ROW_PER_LINE)
1014 # report "ROW_PER_LINE not power of 2" severity FAILURE;
1015 # assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
1016 # report "geometry bits don't add up" severity FAILURE;
1017 # assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
1018 # report "geometry bits don't add up" severity FAILURE;
1019 # assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
1020 # report "geometry bits don't add up" severity FAILURE;
1021 # assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
1022 # report "geometry bits don't add up" severity FAILURE;
1023 # assert (64 = wishbone_data_bits)
1024 # report "Can't yet handle a wishbone width that isn't 64-bits"
1026 # assert SET_SIZE_BITS <= TLB_LG_PGSZ
1027 # report "Set indexed by virtual address" severity FAILURE;
1028 assert (LINE_SIZE
% ROW_SIZE
) == 0 "LINE_SIZE not
1029 multiple of ROW_SIZE -!- severity FAILURE"
1031 assert (LINE_SIZE
% 2) == 0 "LINE_SIZE not power of
1032 2 -!- severity FAILURE"
1034 assert (NUM_LINES
% 2) == 0 "NUM_LINES not power of
1035 2 -!- severity FAILURE"
1037 assert (ROW_PER_LINE
% 2) == 0 "ROW_PER_LINE not
1038 power of 2 -!- severity FAILURE"
1040 assert ROW_BITS
== (INDEX_BITS
+ ROW_LINE_BITS
)
1041 "geometry bits don't add up -!- severity FAILURE"
1043 assert (LINE_OFF_BITS
= ROW_OFF_BITS
+ ROW_LINEBITS
)
1044 "geometry bits don't add up -!- severity FAILURE"
1046 assert REAL_ADDR_BITS
== (TAG_BITS
+ INDEX_BITS
1047 + LINE_OFF_BITS
) "geometry bits don't add up -!-
1050 assert REAL_ADDR_BITS
== (TAG_BITS
+ ROW_BITS
+ ROW_OFF_BITS
)
1051 "geometry bits don't add up -!- severity FAILURE"
1053 assert 64 == wishbone_data_bits
"Can't yet handle a
1054 wishbone width that isn't 64-bits -!- severity FAILURE"
1056 assert SET_SIZE_BITS
<= TLB_LG_PGSZ
"Set indexed by
1057 virtual address -!- severity FAILURE"
1059 # -- Latch the request in r0.req as long as we're not stalling
1060 # stage_0 : process(clk)
1061 # Latch the request in r0.req as long as we're not stalling
1062 class Stage0(Elaboratable
):
1066 def elaborate(self
, platform
):
1072 # variable r : reg_stage_0_t;
1077 # if rising_edge(clk) then
1078 # assert (d_in.valid and m_in.valid) = '0'
1079 # report "request collision loadstore vs MMU";
1080 assert ~
(d_in
.valid
& m_in
.valid
) "request collision
1083 # if m_in.valid = '1' then
1084 with m
.If(m_in
.valid
):
1085 # r.req.valid := '1';
1086 # r.req.load := not (m_in.tlbie or m_in.tlbld);
1087 # r.req.dcbz := '0';
1089 # r.req.reserve := '0';
1090 # r.req.virt_mode := '0';
1091 # r.req.priv_mode := '1';
1092 # r.req.addr := m_in.addr;
1093 # r.req.data := m_in.pte;
1094 # r.req.byte_sel := (others => '1');
1095 # r.tlbie := m_in.tlbie;
1096 # r.doall := m_in.doall;
1097 # r.tlbld := m_in.tlbld;
1099 sync
+= r
.req
.valid
.eq(1)
1100 sync
+= r
.req
.load
.eq(~
(m_in
.tlbie | m_in
.tlbld
))
1101 sync
+= r
.req
.priv_mode
.eq(1)
1102 sync
+= r
.req
.addr
.eq(m_in
.addr
)
1103 sync
+= r
.req
.data
.eq(m_in
.pte
)
1104 sync
+= r
.req
.byte_sel
.eq(1)
1105 sync
+= r
.tlbie
.eq(m_in
.tlbie
)
1106 sync
+= r
.doall
.eq(m_in
.doall
)
1107 sync
+= r
.tlbld
.eq(m_in
.tlbld
)
1108 sync
+= r
.mmu_req
.eq(1)
1116 sync
+= r
.req
.eq(d_in
)
1120 # elsif r1.full = '0' or r0_full = '0' then
1121 with m
.If(~r1
.full | ~r0_full
):
1123 # r0_full <= r.req.valid;
1125 sync
+= r0_full
.eq(r
.req
.valid
)
1130 # -- we don't yet handle collisions between loadstore1 requests
1131 # -- and MMU requests
1132 # m_out.stall <= '0';
1133 # we don't yet handle collisions between loadstore1 requests
1135 comb
+= m_out
.stall
.eq(0)
1137 # -- Hold off the request in r0 when r1 has an uncompleted request
1138 # r0_stall <= r0_full and r1.full;
1139 # r0_valid <= r0_full and not r1.full;
1140 # stall_out <= r0_stall;
1141 # Hold off the request in r0 when r1 has an uncompleted request
1142 comb
+= r0_stall
.eq(r0_full
& r1
.full
)
1143 comb
+= r0_valid
.eq(r0_full
& ~r1
.full
)
1144 comb
+= stall_out
.eq(r0_stall
)
1147 # -- Operates in the second cycle on the request latched in r0.req.
1148 # -- TLB updates write the entry at the end of the second cycle.
1149 # tlb_read : process(clk)
1151 # Operates in the second cycle on the request latched in r0.req.
1152 # TLB updates write the entry at the end of the second cycle.
1153 class TLBRead(Elaboratable
):
1157 def elaborate(self
, platform
):
1163 # variable index : tlb_index_t;
1164 # variable addrbits :
1165 # std_ulogic_vector(TLB_SET_BITS - 1 downto 0);
1166 index
= TLB_SET_SIZE
1167 addrbits
= Signal(TLB_SET_BITS
)
1173 # if rising_edge(clk) then
1174 # if m_in.valid = '1' then
1175 with m
.If(m_in
.valid
):
1176 # addrbits := m_in.addr(TLB_LG_PGSZ + TLB_SET_BITS
1177 # - 1 downto TLB_LG_PGSZ);
1178 sync
+= addrbits
.eq(m_in
.addr
[
1179 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
1183 # addrbits := d_in.addr(TLB_LG_PGSZ + TLB_SET_BITS
1184 # - 1 downto TLB_LG_PGSZ);
1185 sync
+= addrbits
.eq(d_in
.addr
[
1186 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
1190 # index := to_integer(unsigned(addrbits));
1191 sync
+= index
.eq(addrbits
)
1192 # -- If we have any op and the previous op isn't finished,
1193 # -- then keep the same output for next cycle.
1194 # if r0_stall = '0' then
1195 # If we have any op and the previous op isn't finished,
1196 # then keep the same output for next cycle.
1197 with m
.If(~r0_stall
):
1198 sync
+= tlb_valid_way
.eq(dtlb_valids
[index
])
1199 sync
+= tlb_tag_way
.eq(dtlb_tags
[index
])
1200 sync
+= tlb_pte_way
.eq(dtlb_ptes
[index
])
1205 # -- Generate TLB PLRUs
1206 # maybe_tlb_plrus: if TLB_NUM_WAYS > 1 generate
1207 # Generate TLB PLRUs
1208 class MaybeTLBPLRUs(Elaboratable
):
1212 def elaborate(self
, platform
):
1218 with m
.If(TLB_NUM_WAYS
> 1):
1220 # TODO understand how to conver generate statements
1221 # tlb_plrus: for i in 0 to TLB_SET_SIZE - 1 generate
1222 # -- TLB PLRU interface
1223 # signal tlb_plru_acc :
1224 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
1225 # signal tlb_plru_acc_en : std_ulogic;
1226 # signal tlb_plru_out :
1227 # std_ulogic_vector(TLB_WAY_BITS-1 downto 0);
1229 # tlb_plru : entity work.plru
1231 # BITS => TLB_WAY_BITS
1236 # acc => tlb_plru_acc,
1237 # acc_en => tlb_plru_acc_en,
1238 # lru => tlb_plru_out
1244 # if r1.tlb_hit_index = i then
1245 # tlb_plru_acc_en <= r1.tlb_hit;
1247 # tlb_plru_acc_en <= '0';
1250 # std_ulogic_vector(to_unsigned(
1251 # r1.tlb_hit_way, TLB_WAY_BITS
1253 # tlb_plru_victim(i) <= tlb_plru_out;
1259 # tlb_search : process(all)
1260 class TLBSearch(Elaboratable
):
1264 def elborate(self
, platform
):
1270 # variable hitway : tlb_way_t;
1271 # variable hit : std_ulogic;
1272 # variable eatag : tlb_tag_t;
1283 # to_integer(unsigned(r0.req.addr(
1284 # TLB_LG_PGSZ + TLB_SET_BITS - 1 downto TLB_LG_PGSZ
1288 # eatag := r0.req.addr(63 downto TLB_LG_PGSZ + TLB_SET_BITS);
1289 # for i in tlb_way_t loop
1290 # if tlb_valid_way(i) = '1' and
1291 # read_tlb_tag(i, tlb_tag_way) = eatag then
1296 # tlb_hit <= hit and r0_valid;
1297 # tlb_hit_way <= hitway;
1298 comb
+= tlb_req_index
.eq(r0
.req
.addr
[
1299 TLB_LG_PGSZ
:TLB_LG_PGSZ
+ TLB_SET_BITS
1302 comb
+= eatag
.eq(r0
.req
.addr
[
1303 TLB_LG_PGSZ
+ TLB_SET_BITS
:64
1307 with m
.If(tlb_valid_way(i
)
1308 & read_tlb_tag(i
, tlb_tag_way
) == eatag
):
1310 comb
+= hitway
.eq(i
)
1313 comb
+= tlb_hit
.eq(hit
& r0_valid
)
1314 comb
+= tlb_hit_way
.eq(hitway
)
1316 # if tlb_hit = '1' then
1318 # pte <= read_tlb_pte(hitway, tlb_pte_way);
1319 comb
+= pte
.eq(read_tlb_pte(hitway
, tlb_pte_way
))
1322 # pte <= (others => '0');
1325 # valid_ra <= tlb_hit or not r0.req.virt_mode;
1326 comb
+= valid_ra
.eq(tlb_hit | ~r0
.req
.virt_mode
)
1327 # if r0.req.virt_mode = '1' then
1328 with m
.If(r0
.req
.virt_mode
):
1329 # ra <= pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ) &
1330 # r0.req.addr(TLB_LG_PGSZ - 1 downto ROW_OFF_BITS) &
1331 # (ROW_OFF_BITS-1 downto 0 => '0');
1332 # perm_attr <= extract_perm_attr(pte);
1334 Const(ROW_OFF_BITS
, ROW_OFF_BITS
),
1335 r0
.req
.addr
[ROW_OFF_BITS
:TLB_LG_PGSZ
],
1336 pte
[TLB_LG_PGSZ
:REAL_ADDR_BITS
]
1338 comb
+= perm_attr
.eq(extract_perm_attr(pte
))
1341 # ra <= r0.req.addr(
1342 # REAL_ADDR_BITS - 1 downto ROW_OFF_BITS
1343 # ) & (ROW_OFF_BITS-1 downto 0 => '0');
1345 Const(ROW_OFF_BITS
, ROW_OFF_BITS
),
1346 r0
.rq
.addr
[ROW_OFF_BITS
:REAL_ADDR_BITS
]
1349 # perm_attr <= real_mode_perm_attr;
1350 comb
+= perm_attr
.eq(real_mode_perm_attr
)
1354 # tlb_update : process(clk)
1355 class TLBUpdate(Elaboratable
):
1359 def elaborate(self
, platform
):
1365 # variable tlbie : std_ulogic;
1366 # variable tlbwe : std_ulogic;
1367 # variable repl_way : tlb_way_t;
1368 # variable eatag : tlb_tag_t;
1369 # variable tagset : tlb_way_tags_t;
1370 # variable pteset : tlb_way_ptes_t;
1375 tagset
= TLBWayTags()
1376 pteset
= TLBWayPtes()
1386 # if rising_edge(clk) then
1387 # tlbie := r0_valid and r0.tlbie;
1388 # tlbwe := r0_valid and r0.tlbldoi;
1389 sync
+= tlbie
.eq(r0_valid
& r0
.tlbie
)
1390 sync
+= tlbwe
.eq(r0_valid
& r0
.tlbldoi
)
1392 # if rst = '1' or (tlbie = '1' and r0.doall = '1') then
1393 # with m.If (TODO understand how signal resets work in nmigen)
1394 # -- clear all valid bits at once
1395 # for i in tlb_index_t loop
1396 # dtlb_valids(i) <= (others => '0');
1398 # clear all valid bits at once
1399 for i
in range(TLB_SET_SIZE
):
1400 sync
+= dtlb_valids
[i
].eq(0)
1401 # elsif tlbie = '1' then
1403 # if tlb_hit = '1' then
1405 # dtlb_valids(tlb_req_index)(tlb_hit_way) <= '0';
1406 sync
+= dtlb_valids
[tlb_req_index
][tlb_hit_way
].eq(0)
1408 # elsif tlbwe = '1' then
1410 # if tlb_hit = '1' then
1412 # repl_way := tlb_hit_way;
1413 sync
+= repl_way
.eq(tlb_hit_way
)
1416 # repl_way := to_integer(unsigned(
1417 # tlb_plru_victim(tlb_req_index)));
1418 sync
+= repl_way
.eq(tlb_plru_victim
[tlb_req_index
])
1420 # eatag := r0.req.addr(
1421 # 63 downto TLB_LG_PGSZ + TLB_SET_BITS
1423 # tagset := tlb_tag_way;
1424 # write_tlb_tag(repl_way, tagset, eatag);
1425 # dtlb_tags(tlb_req_index) <= tagset;
1426 # pteset := tlb_pte_way;
1427 # write_tlb_pte(repl_way, pteset, r0.req.data);
1428 # dtlb_ptes(tlb_req_index) <= pteset;
1429 # dtlb_valids(tlb_req_index)(repl_way) <= '1';
1430 sync
+= eatag
.eq(r0
.req
.addr
[TLB_LG_PGSZ
+ TLB_SET_BITS
:64])
1431 sync
+= tagset
.eq(tlb_tag_way
)
1432 sync
+= write_tlb_tag(repl_way
, tagset
, eatag
)
1433 sync
+= dtlb_tags
[tlb_req_index
].eq(tagset
)
1434 sync
+= pteset
.eq(tlb_pte_way
)
1435 sync
+= write_tlb_pte(repl_way
, pteset
, r0
.req
.data
)
1436 sync
+= dtlb_ptes
[tlb_req_index
].eq(pteset
)
1437 sync
+= dtlb_valids
[tlb_req_index
][repl_way
].eq(1)
1443 # maybe_plrus: if NUM_WAYS > 1 generate
1444 class MaybePLRUs(Elaboratable
):
1448 def elaborate(self
, platform
):
1455 # TODO learn translation of generate into nmgien @lkcl
1456 # plrus: for i in 0 to NUM_LINES-1 generate
1458 # signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
1459 # signal plru_acc_en : std_ulogic;
1460 # signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
1463 # TODO learn tranlation of entity, generic map, port map in
1465 # plru : entity work.plru
1473 # acc_en => plru_acc_en,
1480 # if r1.hit_index = i then
1481 # plru_acc_en <= r1.cache_hit;
1483 # plru_acc_en <= '0';
1485 # plru_acc <= std_ulogic_vector(to_unsigned(
1486 # r1.hit_way, WAY_BITS
1488 # plru_victim(i) <= plru_out;
1493 # -- Cache tag RAM read port
1494 # cache_tag_read : process(clk)
1495 # variable index : index_t;
1497 # if rising_edge(clk) then
1498 # if r0_stall = '1' then
1499 # index := req_index;
1500 # elsif m_in.valid = '1' then
1501 # index := get_index(m_in.addr);
1503 # index := get_index(d_in.addr);
1505 # cache_tag_set <= cache_tags(index);
1509 # -- Cache request parsing and hit detection
1510 # dcache_request : process(all)
1511 # variable is_hit : std_ulogic;
1512 # variable hit_way : way_t;
1513 # variable op : op_t;
1514 # variable opsel : std_ulogic_vector(2 downto 0);
1515 # variable go : std_ulogic;
1516 # variable nc : std_ulogic;
1517 # variable s_hit : std_ulogic;
1518 # variable s_tag : cache_tag_t;
1519 # variable s_pte : tlb_pte_t;
1520 # variable s_ra : std_ulogic_vector(
1521 # REAL_ADDR_BITS - 1 downto 0
1523 # variable hit_set : std_ulogic_vector(
1524 # TLB_NUM_WAYS - 1 downto 0
1526 # variable hit_way_set : hit_way_set_t;
1527 # variable rel_matches : std_ulogic_vector(
1528 # TLB_NUM_WAYS - 1 downto 0
1530 # variable rel_match : std_ulogic;
1532 # -- Extract line, row and tag from request
1533 # req_index <= get_index(r0.req.addr);
1534 # req_row <= get_row(r0.req.addr);
1535 # req_tag <= get_tag(ra);
1537 # go := r0_valid and not (r0.tlbie or r0.tlbld)
1538 # and not r1.ls_error;
1540 # -- Test if pending request is a hit on any way
1541 # -- In order to make timing in virtual mode,
1542 # -- when we are using the TLB, we compare each
1543 # --way with each of the real addresses from each way of
1544 # -- the TLB, and then decide later which match to use.
1548 # if r0.req.virt_mode = '1' then
1549 # rel_matches := (others => '0');
1550 # for j in tlb_way_t loop
1551 # hit_way_set(j) := 0;
1553 # s_pte := read_tlb_pte(j, tlb_pte_way);
1555 # s_pte(REAL_ADDR_BITS - 1 downto TLB_LG_PGSZ)
1556 # & r0.req.addr(TLB_LG_PGSZ - 1 downto 0);
1557 # s_tag := get_tag(s_ra);
1558 # for i in way_t loop
1559 # if go = '1' and cache_valids(req_index)(i) = '1'
1560 # and read_tag(i, cache_tag_set) = s_tag
1561 # and tlb_valid_way(j) = '1' then
1562 # hit_way_set(j) := i;
1566 # hit_set(j) := s_hit;
1567 # if s_tag = r1.reload_tag then
1568 # rel_matches(j) := '1';
1571 # if tlb_hit = '1' then
1572 # is_hit := hit_set(tlb_hit_way);
1573 # hit_way := hit_way_set(tlb_hit_way);
1574 # rel_match := rel_matches(tlb_hit_way);
1577 # s_tag := get_tag(r0.req.addr);
1578 # for i in way_t loop
1579 # if go = '1' and cache_valids(req_index)(i) = '1' and
1580 # read_tag(i, cache_tag_set) = s_tag then
1585 # if s_tag = r1.reload_tag then
1589 # req_same_tag <= rel_match;
1591 # -- See if the request matches the line currently being reloaded
1592 # if r1.state = RELOAD_WAIT_ACK and req_index = r1.store_index
1593 # and rel_match = '1' then
1594 # -- For a store, consider this a hit even if the row isn't
1595 # -- valid since it will be by the time we perform the store.
1596 # -- For a load, check the appropriate row valid bit.
1598 # not r0.req.load or r1.rows_valid(req_row mod ROW_PER_LINE);
1599 # hit_way := replace_way;
1602 # -- Whether to use forwarded data for a load or not
1603 # use_forward1_next <= '0';
1604 # if get_row(r1.req.real_addr) = req_row
1605 # and r1.req.hit_way = hit_way then
1606 # -- Only need to consider r1.write_bram here, since if we
1607 # -- are writing refill data here, then we don't have a
1608 # -- cache hit this cycle on the line being refilled.
1609 # -- (There is the possibility that the load following the
1610 # -- load miss that started the refill could be to the old
1611 # -- contents of the victim line, since it is a couple of
1612 # -- cycles after the refill starts before we see the updated
1613 # -- cache tag. In that case we don't use the bypass.)
1614 # use_forward1_next <= r1.write_bram;
1616 # use_forward2_next <= '0';
1617 # if r1.forward_row1 = req_row and r1.forward_way1 = hit_way then
1618 # use_forward2_next <= r1.forward_valid1;
1621 # -- The way that matched on a hit
1622 # req_hit_way <= hit_way;
1624 # -- The way to replace on a miss
1625 # if r1.write_tag = '1' then
1626 # replace_way <= to_integer(unsigned(
1627 # plru_victim(r1.store_index)
1630 # replace_way <= r1.store_way;
1633 # -- work out whether we have permission for this access
1634 # -- NB we don't yet implement AMR, thus no KUAP
1635 # rc_ok <= perm_attr.reference and
1636 # (r0.req.load or perm_attr.changed);
1637 # perm_ok <= (r0.req.priv_mode or not perm_attr.priv) and
1638 # (perm_attr.wr_perm or (r0.req.load
1639 # and perm_attr.rd_perm));
1640 # access_ok <= valid_ra and perm_ok and rc_ok;
1642 # -- Combine the request and cache hit status to decide what
1643 # -- operation needs to be done
1645 # nc := r0.req.nc or perm_attr.nocache;
1648 # if access_ok = '0' then
1650 # elsif cancel_store = '1' then
1651 # op := OP_STCX_FAIL;
1653 # opsel := r0.req.load & nc & is_hit;
1655 # when "101" => op := OP_LOAD_HIT;
1656 # when "100" => op := OP_LOAD_MISS;
1657 # when "110" => op := OP_LOAD_NC;
1658 # when "001" => op := OP_STORE_HIT;
1659 # when "000" => op := OP_STORE_MISS;
1660 # when "010" => op := OP_STORE_MISS;
1661 # when "011" => op := OP_BAD;
1662 # when "111" => op := OP_BAD;
1663 # when others => op := OP_NONE;
1670 # -- Version of the row number that is valid one cycle earlier
1671 # -- in the cases where we need to read the cache data BRAM.
1672 # -- If we're stalling then we need to keep reading the last
1674 # if r0_stall = '0' then
1675 # if m_in.valid = '1' then
1676 # early_req_row <= get_row(m_in.addr);
1678 # early_req_row <= get_row(d_in.addr);
1681 # early_req_row <= req_row;
1685 # -- Wire up wishbone request latch out of stage 1
1686 # wishbone_out <= r1.wb;
1688 # -- Handle load-with-reservation and store-conditional instructions
1689 # reservation_comb: process(all)
1691 # cancel_store <= '0';
1693 # clear_rsrv <= '0';
1694 # if r0_valid = '1' and r0.req.reserve = '1' then
1695 # -- XXX generate alignment interrupt if address
1696 # -- is not aligned XXX or if r0.req.nc = '1'
1697 # if r0.req.load = '1' then
1698 # -- load with reservation
1701 # -- store conditional
1702 # clear_rsrv <= '1';
1703 # if reservation.valid = '0' or r0.req.addr(63
1704 # downto LINE_OFF_BITS) /= reservation.addr then
1705 # cancel_store <= '1';
1711 # reservation_reg: process(clk)
1713 # if rising_edge(clk) then
1715 # reservation.valid <= '0';
1716 # elsif r0_valid = '1' and access_ok = '1' then
1717 # if clear_rsrv = '1' then
1718 # reservation.valid <= '0';
1719 # elsif set_rsrv = '1' then
1720 # reservation.valid <= '1';
1721 # reservation.addr <=
1722 # r0.req.addr(63 downto LINE_OFF_BITS);
1728 # -- Return data for loads & completion control logic
1730 # writeback_control: process(all)
1731 # variable data_out : std_ulogic_vector(63 downto 0);
1732 # variable data_fwd : std_ulogic_vector(63 downto 0);
1733 # variable j : integer;
1735 # -- Use the bypass if are reading the row that was
1736 # -- written 1 or 2 cycles ago, including for the
1737 # -- slow_valid = 1 case (i.e. completing a load
1738 # -- miss or a non-cacheable load).
1739 # if r1.use_forward1 = '1' then
1740 # data_fwd := r1.forward_data1;
1742 # data_fwd := r1.forward_data2;
1744 # data_out := cache_out(r1.hit_way);
1745 # for i in 0 to 7 loop
1747 # if r1.forward_sel(i) = '1' then
1748 # data_out(j + 7 downto j) := data_fwd(j + 7 downto j);
1752 # d_out.valid <= r1.ls_valid;
1753 # d_out.data <= data_out;
1754 # d_out.store_done <= not r1.stcx_fail;
1755 # d_out.error <= r1.ls_error;
1756 # d_out.cache_paradox <= r1.cache_paradox;
1759 # m_out.done <= r1.mmu_done;
1760 # m_out.err <= r1.mmu_error;
1761 # m_out.data <= data_out;
1763 # -- We have a valid load or store hit or we just completed
1764 # -- a slow op such as a load miss, a NC load or a store
1766 # -- Note: the load hit is delayed by one cycle. However it
1767 # -- can still not collide with r.slow_valid (well unless I
1768 # -- miscalculated) because slow_valid can only be set on a
1769 # -- subsequent request and not on its first cycle (the state
1770 # -- machine must have advanced), which makes slow_valid
1771 # -- at least 2 cycles from the previous hit_load_valid.
1773 # -- Sanity: Only one of these must be set in any given cycle
1774 # assert (r1.slow_valid and r1.stcx_fail) /= '1'
1775 # report "unexpected slow_valid collision with stcx_fail"
1777 # assert ((r1.slow_valid or r1.stcx_fail) and r1.hit_load_valid)
1778 # /= '1' report "unexpected hit_load_delayed collision with
1779 # slow_valid" severity FAILURE;
1781 # if r1.mmu_req = '0' then
1782 # -- Request came from loadstore1...
1783 # -- Load hit case is the standard path
1784 # if r1.hit_load_valid = '1' then
1786 # "completing load hit data=" & to_hstring(data_out);
1789 # -- error cases complete without stalling
1790 # if r1.ls_error = '1' then
1791 # report "completing ld/st with error";
1794 # -- Slow ops (load miss, NC, stores)
1795 # if r1.slow_valid = '1' then
1797 # "completing store or load miss data="
1798 # & to_hstring(data_out);
1802 # -- Request came from MMU
1803 # if r1.hit_load_valid = '1' then
1804 # report "completing load hit to MMU, data="
1805 # & to_hstring(m_out.data);
1808 # -- error cases complete without stalling
1809 # if r1.mmu_error = '1' then
1810 # report "completing MMU ld with error";
1813 # -- Slow ops (i.e. load miss)
1814 # if r1.slow_valid = '1' then
1815 # report "completing MMU load miss, data="
1816 # & to_hstring(m_out.data);
1823 # -- Generate a cache RAM for each way. This handles the normal
1824 # -- reads, writes from reloads and the special store-hit update
1827 # -- Note: the BRAMs have an extra read buffer, meaning the output
1828 # -- is pipelined an extra cycle. This differs from the
1829 # -- icache. The writeback logic needs to take that into
1830 # -- account by using 1-cycle delayed signals for load hits.
1832 # rams: for i in 0 to NUM_WAYS-1 generate
1833 # signal do_read : std_ulogic;
1834 # signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1835 # signal do_write : std_ulogic;
1836 # signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
1838 # std_ulogic_vector(wishbone_data_bits-1 downto 0);
1839 # signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
1840 # signal wr_sel_m : std_ulogic_vector(ROW_SIZE-1 downto 0);
1841 # signal dout : cache_row_t;
1843 # way: entity work.cache_ram
1845 # ROW_BITS => ROW_BITS,
1846 # WIDTH => wishbone_data_bits,
1852 # rd_addr => rd_addr,
1854 # wr_sel => wr_sel_m,
1855 # wr_addr => wr_addr,
1856 # wr_data => wr_data
1860 # -- Cache hit reads
1863 # std_ulogic_vector(to_unsigned(early_req_row, ROW_BITS));
1864 # cache_out(i) <= dout;
1868 # -- Defaults to wishbone read responses (cache refill)
1870 # -- For timing, the mux on wr_data/sel/addr is not
1871 # -- dependent on anything other than the current state.
1872 # wr_sel_m <= (others => '0');
1875 # if r1.write_bram = '1' then
1876 # -- Write store data to BRAM. This happens one
1877 # -- cycle after the store is in r0.
1878 # wr_data <= r1.req.data;
1879 # wr_sel <= r1.req.byte_sel;
1880 # wr_addr <= std_ulogic_vector(to_unsigned(
1881 # get_row(r1.req.real_addr), ROW_BITS
1883 # if i = r1.req.hit_way then
1887 # -- Otherwise, we might be doing a reload or a DCBZ
1888 # if r1.dcbz = '1' then
1889 # wr_data <= (others => '0');
1891 # wr_data <= wishbone_in.dat;
1893 # wr_addr <= std_ulogic_vector(to_unsigned(
1894 # r1.store_row, ROW_BITS
1896 # wr_sel <= (others => '1');
1898 # if r1.state = RELOAD_WAIT_ACK and
1899 # wishbone_in.ack = '1' and replace_way = i then
1904 # -- Mask write selects with do_write since BRAM
1905 # -- doesn't have a global write-enable
1906 # if do_write = '1' then
1907 # wr_sel_m <= wr_sel;
1913 # -- Cache hit synchronous machine for the easy case.
1914 # -- This handles load hits.
1915 # -- It also handles error cases (TLB miss, cache paradox)
1916 # dcache_fast_hit : process(clk)
1918 # if rising_edge(clk) then
1919 # if req_op /= OP_NONE then
1920 # report "op:" & op_t'image(req_op) &
1921 # " addr:" & to_hstring(r0.req.addr) &
1922 # " nc:" & std_ulogic'image(r0.req.nc) &
1923 # " idx:" & integer'image(req_index) &
1924 # " tag:" & to_hstring(req_tag) &
1925 # " way: " & integer'image(req_hit_way);
1927 # if r0_valid = '1' then
1928 # r1.mmu_req <= r0.mmu_req;
1931 # -- Fast path for load/store hits.
1932 # -- Set signals for the writeback controls.
1933 # r1.hit_way <= req_hit_way;
1934 # r1.hit_index <= req_index;
1935 # if req_op = OP_LOAD_HIT then
1936 # r1.hit_load_valid <= '1';
1938 # r1.hit_load_valid <= '0';
1940 # if req_op = OP_LOAD_HIT or req_op = OP_STORE_HIT then
1941 # r1.cache_hit <= '1';
1943 # r1.cache_hit <= '0';
1946 # if req_op = OP_BAD then
1947 # report "Signalling ld/st error valid_ra=" &
1948 # std_ulogic'image(valid_ra) & " rc_ok=" &
1949 # std_ulogic'image(rc_ok) & " perm_ok=" &
1950 # std_ulogic'image(perm_ok);
1951 # r1.ls_error <= not r0.mmu_req;
1952 # r1.mmu_error <= r0.mmu_req;
1953 # r1.cache_paradox <= access_ok;
1955 # r1.ls_error <= '0';
1956 # r1.mmu_error <= '0';
1957 # r1.cache_paradox <= '0';
1960 # if req_op = OP_STCX_FAIL then
1961 # r1.stcx_fail <= '1';
1963 # r1.stcx_fail <= '0';
1966 # -- Record TLB hit information for updating TLB PLRU
1967 # r1.tlb_hit <= tlb_hit;
1968 # r1.tlb_hit_way <= tlb_hit_way;
1969 # r1.tlb_hit_index <= tlb_req_index;
1974 # -- Memory accesses are handled by this state machine:
1976 # -- * Cache load miss/reload (in conjunction with "rams")
1977 # -- * Load hits for non-cachable forms
1978 # -- * Stores (the collision case is handled in "rams")
1980 # -- All wishbone requests generation is done here.
1981 # -- This machine operates at stage 1.
1982 # dcache_slow : process(clk)
1983 # variable stbs_done : boolean;
1984 # variable req : mem_access_request_t;
1985 # variable acks : unsigned(2 downto 0);
1987 # if rising_edge(clk) then
1988 # r1.use_forward1 <= use_forward1_next;
1989 # r1.forward_sel <= (others => '0');
1990 # if use_forward1_next = '1' then
1991 # r1.forward_sel <= r1.req.byte_sel;
1992 # elsif use_forward2_next = '1' then
1993 # r1.forward_sel <= r1.forward_sel1;
1996 # r1.forward_data2 <= r1.forward_data1;
1997 # if r1.write_bram = '1' then
1998 # r1.forward_data1 <= r1.req.data;
1999 # r1.forward_sel1 <= r1.req.byte_sel;
2000 # r1.forward_way1 <= r1.req.hit_way;
2001 # r1.forward_row1 <= get_row(r1.req.real_addr);
2002 # r1.forward_valid1 <= '1';
2004 # if r1.dcbz = '1' then
2005 # r1.forward_data1 <= (others => '0');
2007 # r1.forward_data1 <= wishbone_in.dat;
2009 # r1.forward_sel1 <= (others => '1');
2010 # r1.forward_way1 <= replace_way;
2011 # r1.forward_row1 <= r1.store_row;
2012 # r1.forward_valid1 <= '0';
2015 # -- On reset, clear all valid bits to force misses
2017 # for i in index_t loop
2018 # cache_valids(i) <= (others => '0');
2022 # r1.slow_valid <= '0';
2025 # r1.ls_valid <= '0';
2026 # r1.mmu_done <= '0';
2028 # -- Not useful normally but helps avoiding
2029 # -- tons of sim warnings
2030 # r1.wb.adr <= (others => '0');
2032 # -- One cycle pulses reset
2033 # r1.slow_valid <= '0';
2034 # r1.write_bram <= '0';
2035 # r1.inc_acks <= '0';
2036 # r1.dec_acks <= '0';
2038 # r1.ls_valid <= '0';
2039 # -- complete tlbies and TLB loads in the third cycle
2040 # r1.mmu_done <= r0_valid and (r0.tlbie or r0.tlbld);
2041 # if req_op = OP_LOAD_HIT or req_op = OP_STCX_FAIL then
2042 # if r0.mmu_req = '0' then
2043 # r1.ls_valid <= '1';
2045 # r1.mmu_done <= '1';
2049 # if r1.write_tag = '1' then
2050 # -- Store new tag in selected way
2051 # for i in 0 to NUM_WAYS-1 loop
2052 # if i = replace_way then
2053 # cache_tags(r1.store_index)(
2054 # (i + 1) * TAG_WIDTH - 1
2055 # downto i * TAG_WIDTH
2057 # (TAG_WIDTH - 1 downto TAG_BITS => '0')
2061 # r1.store_way <= replace_way;
2062 # r1.write_tag <= '0';
2065 # -- Take request from r1.req if there is one there,
2066 # -- else from req_op, ra, etc.
2067 # if r1.full = '1' then
2071 # req.valid := req_go;
2072 # req.mmu_req := r0.mmu_req;
2073 # req.dcbz := r0.req.dcbz;
2074 # req.real_addr := ra;
2075 # -- Force data to 0 for dcbz
2076 # if r0.req.dcbz = '0' then
2077 # req.data := r0.req.data;
2079 # req.data := (others => '0');
2081 # -- Select all bytes for dcbz
2082 # -- and for cacheable loads
2083 # if r0.req.dcbz = '1'
2084 # or (r0.req.load = '1' and r0.req.nc = '0') then
2085 # req.byte_sel := (others => '1');
2087 # req.byte_sel := r0.req.byte_sel;
2089 # req.hit_way := req_hit_way;
2090 # req.same_tag := req_same_tag;
2092 # -- Store the incoming request from r0,
2093 # -- if it is a slow request
2094 # -- Note that r1.full = 1 implies req_op = OP_NONE
2095 # if req_op = OP_LOAD_MISS or req_op = OP_LOAD_NC
2096 # or req_op = OP_STORE_MISS
2097 # or req_op = OP_STORE_HIT then
2103 # -- Main state machine
2106 # r1.wb.adr <= req.real_addr(r1.wb.adr'left downto 0);
2107 # r1.wb.sel <= req.byte_sel;
2108 # r1.wb.dat <= req.data;
2109 # r1.dcbz <= req.dcbz;
2111 # -- Keep track of our index and way
2112 # -- for subsequent stores.
2113 # r1.store_index <= get_index(req.real_addr);
2114 # r1.store_row <= get_row(req.real_addr);
2116 # get_row_of_line(get_row(req.real_addr)) - 1;
2117 # r1.reload_tag <= get_tag(req.real_addr);
2118 # r1.req.same_tag <= '1';
2120 # if req.op = OP_STORE_HIT then
2121 # r1.store_way <= req.hit_way;
2124 # -- Reset per-row valid bits,
2125 # -- ready for handling OP_LOAD_MISS
2126 # for i in 0 to ROW_PER_LINE - 1 loop
2127 # r1.rows_valid(i) <= '0';
2131 # when OP_LOAD_HIT =>
2132 # -- stay in IDLE state
2134 # when OP_LOAD_MISS =>
2135 # -- Normal load cache miss,
2136 # -- start the reload machine
2137 # report "cache miss real addr:" &
2138 # to_hstring(req.real_addr) & " idx:" &
2139 # integer'image(get_index(req.real_addr)) &
2140 # " tag:" & to_hstring(get_tag(req.real_addr));
2142 # -- Start the wishbone cycle
2147 # -- Track that we had one request sent
2148 # r1.state <= RELOAD_WAIT_ACK;
2149 # r1.write_tag <= '1';
2151 # when OP_LOAD_NC =>
2155 # r1.state <= NC_LOAD_WAIT_ACK;
2157 # when OP_STORE_HIT | OP_STORE_MISS =>
2158 # if req.dcbz = '0' then
2159 # r1.state <= STORE_WAIT_ACK;
2160 # r1.acks_pending <= to_unsigned(1, 3);
2162 # r1.slow_valid <= '1';
2163 # if req.mmu_req = '0' then
2164 # r1.ls_valid <= '1';
2166 # r1.mmu_done <= '1';
2168 # if req.op = OP_STORE_HIT then
2169 # r1.write_bram <= '1';
2172 # -- dcbz is handled much like a load
2173 # -- miss except that we are writing
2174 # -- to memory instead of reading
2175 # r1.state <= RELOAD_WAIT_ACK;
2176 # if req.op = OP_STORE_MISS then
2177 # r1.write_tag <= '1';
2184 # -- OP_NONE and OP_BAD do nothing
2185 # -- OP_BAD & OP_STCX_FAIL were handled above already
2188 # when OP_STCX_FAIL =>
2191 # when RELOAD_WAIT_ACK =>
2192 # -- Requests are all sent if stb is 0
2193 # stbs_done := r1.wb.stb = '0';
2195 # -- If we are still sending requests,
2196 # -- was one accepted?
2197 # if wishbone_in.stall = '0' and not stbs_done then
2198 # -- That was the last word ? We are done sending.
2199 # -- Clear stb and set stbs_done so we can handle
2200 # -- an eventual last ack on the same cycle.
2201 # if is_last_row_addr(r1.wb.adr, r1.end_row_ix) then
2203 # stbs_done := true;
2206 # -- Calculate the next row address
2207 # r1.wb.adr <= next_row_addr(r1.wb.adr);
2210 # -- Incoming acks processing
2211 # r1.forward_valid1 <= wishbone_in.ack;
2212 # if wishbone_in.ack = '1' then
2214 # r1.store_row mod ROW_PER_LINE
2216 # -- If this is the data we were looking for,
2217 # -- we can complete the request next cycle.
2218 # -- Compare the whole address in case the
2219 # -- request in r1.req is not the one that
2220 # -- started this refill.
2221 # if r1.full = '1' and r1.req.same_tag = '1'
2222 # and ((r1.dcbz = '1' and r1.req.dcbz = '1')
2223 # or (r1.dcbz = '0' and r1.req.op = OP_LOAD_MISS))
2224 # and r1.store_row = get_row(r1.req.real_addr) then
2226 # r1.slow_valid <= '1';
2227 # if r1.mmu_req = '0' then
2228 # r1.ls_valid <= '1';
2230 # r1.mmu_done <= '1';
2232 # r1.forward_sel <= (others => '1');
2233 # r1.use_forward1 <= '1';
2236 # -- Check for completion
2237 # if stbs_done and is_last_row(r1.store_row,
2238 # r1.end_row_ix) then
2239 # -- Complete wishbone cycle
2242 # -- Cache line is now valid
2243 # cache_valids(r1.store_index)(
2250 # -- Increment store row counter
2251 # r1.store_row <= next_row(r1.store_row);
2254 # when STORE_WAIT_ACK =>
2255 # stbs_done := r1.wb.stb = '0';
2256 # acks := r1.acks_pending;
2257 # if r1.inc_acks /= r1.dec_acks then
2258 # if r1.inc_acks = '1' then
2264 # r1.acks_pending <= acks;
2265 # -- Clear stb when slave accepted request
2266 # if wishbone_in.stall = '0' then
2267 # -- See if there is another store waiting
2268 # -- to be done which is in the same real page.
2269 # if req.valid = '1' then
2271 # SET_SIZE_BITS - 1 downto 0
2272 # ) <= req.real_addr(
2273 # SET_SIZE_BITS - 1 downto 0
2275 # r1.wb.dat <= req.data;
2276 # r1.wb.sel <= req.byte_sel;
2278 # if acks < 7 and req.same_tag = '1'
2279 # and (req.op = OP_STORE_MISS
2280 # or req.op = OP_STORE_HIT) then
2282 # stbs_done := false;
2283 # if req.op = OP_STORE_HIT then
2284 # r1.write_bram <= '1';
2287 # r1.slow_valid <= '1';
2288 # -- Store requests never come from the MMU
2289 # r1.ls_valid <= '1';
2290 # stbs_done := false;
2291 # r1.inc_acks <= '1';
2294 # stbs_done := true;
2298 # -- Got ack ? See if complete.
2299 # if wishbone_in.ack = '1' then
2300 # if stbs_done and acks = 1 then
2305 # r1.dec_acks <= '1';
2308 # when NC_LOAD_WAIT_ACK =>
2309 # -- Clear stb when slave accepted request
2310 # if wishbone_in.stall = '0' then
2314 # -- Got ack ? complete.
2315 # if wishbone_in.ack = '1' then
2318 # r1.slow_valid <= '1';
2319 # if r1.mmu_req = '0' then
2320 # r1.ls_valid <= '1';
2322 # r1.mmu_done <= '1';
2324 # r1.forward_sel <= (others => '1');
2325 # r1.use_forward1 <= '1';
2334 # dc_log: if LOG_LENGTH > 0 generate
2335 # signal log_data : std_ulogic_vector(19 downto 0);
2337 # dcache_log: process(clk)
2339 # if rising_edge(clk) then
2340 # log_data <= r1.wb.adr(5 downto 3) &
2341 # wishbone_in.stall &
2343 # r1.wb.stb & r1.wb.cyc &
2346 # std_ulogic_vector(
2347 # to_unsigned(op_t'pos(req_op), 3)) &
2349 # std_ulogic_vector(
2350 # to_unsigned(tlb_hit_way, 3)) &
2352 # std_ulogic_vector(
2353 # to_unsigned(state_t'pos(r1.state), 3));
2356 # log_out <= log_data;