3 based on Anton Blanchard microwatt common.vhdl
6 from nmutil
.iocontrol
import RecordObject
7 from nmigen
import Signal
10 class LoadStore1ToMmuType(RecordObject
):
20 self
.sprn
= Signal(10)
21 self
.addr
= Signal(64)
25 class MmuToLoadStore1Type(RecordObject
):
30 self
.invalid
= Signal()
31 self
.badtree
= Signal()
32 self
.segerr
= Signal()
33 self
.perm_error
= Signal()
34 self
.rc_error
= Signal()
35 self
.sprval
= Signal(64)
38 class MmuToDcacheType(RecordObject
):
45 self
.addr
= Signal(64)
49 class DcacheToMmuType(RecordObject
):
55 self
.data
= Signal(64)
59 class MmuToIcacheType(RecordObject
):
65 self
.addr
= Signal(64)
69 class LoadStore1ToDcacheType(RecordObject
):
73 self
.load
= Signal() # this is a load
77 self
.reserve
= Signal()
78 self
.virt_mode
= Signal()
79 self
.priv_mode
= Signal()
82 self
.byte_sel
= Signal()
85 class DcacheToLoadStore1Type(RecordObject
):
90 self
.store_done
= Signal()
92 self
.cache_paradox
= Signal()