src/soc/experiment/pi2ls.py

   1 """
   2     PortInterface                LoadStoreUnitInterface
   3
   4     is_ld_i/1                    x_ld_i
   5     is_st_i/1                    x_st_i
   6
   7     data_len/4                   x_mask/16  (translate using LenExpand)
   8
   9     busy_o/1                     most likely to be x_busy_o
  10     go_die_i/1                   rst?
  11     addr.data/48                 x_addr_i[4:] (x_addr_i[:4] goes into LenExpand)
  12     addr.ok/1                    probably x_valid_i & ~x_stall_i
  13
  14     addr_ok_o/1                  no equivalent.  *might* work using x_stall_i
  15     addr_exc_o/2(?)              m_load_err_o and m_store_err_o
  16
  17     ld.data/64                   m_ld_data_o
  18     ld.ok/1                      probably implicit, when x_busy drops low
  19     st.data/64                   x_st_data_i
  20     st.ok/1                      probably kinda redundant, set to x_st_i
  21 """
  22
  23 from soc.minerva.units.loadstore import LoadStoreUnitInterface
  24 from soc.experiment.pimem import PortInterface
  25 from nmigen import Elaboratable, Module, Signal
  26
  27 class Pi2LSUI(Elaboratable):
  28
  29     def __init__(self, name, regwid=64, addrwid=48):
  30         self.pi = PortInterface(name="%s_pi", regwid, addrwid)
  31         self.lsui = LoadStoreUnitInterface(addrwid, 4, regwid)
  32
  33     def elaborate(self, platform):
  34         m = Module()
  35         return m