src/soc/experiment/plru.py

   1 # based on microwatt plru.vhdl
   2
   3 from nmigen import Elaboratable, Signal, Array, Module
   4
   5 class PLRU(Elaboratable):
   6
   7     def __init__(self, BITS=2):
   8         self.BITS = BITS
   9         self.acc = Signal(BITS)
  10         self.acc_en = Signal()
  11         self.lru_o = Signal(BITS)
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15
  16         tree = Array(Signal() for i in range(self.BITS))
  17
  18         # XXX Check if we can turn that into a little ROM instead that
  19         # takes the tree bit vector and returns the LRU. See if it's better
  20         # in term of FPGA resouces usage...
  21         node = Signal(self.BITS)
  22         for i in range(self.BITS):
  23             node_next = Signal(self.BITS)
  24             node2 = Signal(self.BITS)
  25             # report "GET: i:" & integer'image(i) & " node:" &
  26             # integer'image(node) & " val:" & Signal()'image(tree(node))
  27             comb += self.lru_o[self.BITS-1-i].eq(tree[node])
  28             if i != BITS-1:
  29                 comb += node2.eq(node << 1)
  30             else:
  31                 comb += node2.eq(node)
  32             with m.If(tree[node]):
  33                 comb += node_next.eq(node2 + 2)
  34             with m.Else():
  35                 comb += node_next.eq(node2 + 1)
  36             node = node_next
  37
  38         with m.If(self.acc_en):
  39             node = Signal(self.BITS)
  40             for i in range(self.BITS):
  41                 node_next = Signal(self.BITS)
  42                 node2 = Signal(self.BITS)
  43                 # report "GET: i:" & integer'image(i) & " node:" &
  44                 # integer'image(node) & " val:" & Signal()'image(tree(node))
  45                 abit = self.acc[self.BITS-1-i]
  46                 sync += tree[node].eq(~abit)
  47                 if i != BITS-1:
  48                     comb += node2.eq(node << 1)
  49                 else:
  50                     comb += node2.eq(node)
  51                 with m.If(abit):
  52                     comb += node_next.eq(node2 + 2)
  53                 with m.Else():
  54                     comb += node_next.eq(node2 + 1)
  55                 node = node_next
  56
  57         return m