src/soc/experiment/test/test_compalu_multi.py

   1 """Computation Unit (aka "ALU Manager").
   2
   3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
   4 monitored.  At no time may the ALU proceed without this module notifying
   5 the Dependency Matrices.  At no time is a result production "abandoned".
   6 This module blocks (indicates busy) starting from when it first receives
   7 an opcode until it receives notification that
   8 its result(s) have been successfully stored in the regfile(s)
   9
  10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
  11 """
  12
  13 from soc.experiment.alu_fsm import Shifter, CompFSMOpSubset
  14 from soc.fu.alu.alu_input_record import CompALUOpSubset
  15 from soc.fu.cr.cr_input_record import CompCROpSubset
  16 from soc.experiment.alu_hier import ALU, DummyALU
  17 from soc.experiment.compalu_multi import MultiCompUnit
  18 from soc.decoder.power_enums import MicrOp
  19 from nmutil.gtkw import write_gtkw
  20 from nmigen import Module, Signal
  21 from nmigen.cli import rtlil
  22
  23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  25 from nmutil.sim_tmp_alternative import (Simulator, Settle, is_engine_pysim,
  26                                         Passive)
  27
  28
  29 def wrap(process):
  30     def wrapper():
  31         yield from process
  32     return wrapper
  33
  34
  35 class OperandProducer:
  36     """
  37     Produces an operand when requested by the Computation Unit
  38     (`dut` parameter), using the `rel_o` / `go_i` handshake.
  39
  40     Attaches itself to the `dut` operand indexed by `op_index`.
  41
  42     Has a programmable delay between the assertion of `rel_o` and the
  43     `go_i` pulse.
  44
  45     Data is presented only during the cycle in which `go_i` is active.
  46
  47     It adds itself as a passive process to the simulation (`sim` parameter).
  48     Since it is passive, it will not hang the simulation, and does not need a
  49     flag to terminate itself.
  50     """
  51     def __init__(self, sim, dut, op_index):
  52         self.count = Signal(8, name=f"src{op_index + 1}_count")
  53         """ transaction counter"""
  54         # data and handshake signals from the DUT
  55         self.port = dut.src_i[op_index]
  56         self.go_i = dut.rd.go_i[op_index]
  57         self.rel_o = dut.rd.rel_o[op_index]
  58         # transaction parameters, passed via signals
  59         self.delay = Signal(8)
  60         self.data = Signal.like(self.port)
  61         # add ourselves to the simulation process list
  62         sim.add_sync_process(self._process)
  63
  64     def _process(self):
  65         yield Passive()
  66         while True:
  67             # Settle() is needed to give a quick response to
  68             # the zero delay case
  69             yield Settle()
  70             # wait for rel_o to become active
  71             while not (yield self.rel_o):
  72                 yield
  73                 yield Settle()
  74             # read the transaction parameters
  75             delay = (yield self.delay)
  76             data = (yield self.data)
  77             # wait for `delay` cycles
  78             for _ in range(delay):
  79                 yield
  80             # activate go_i and present data, for one cycle
  81             yield self.go_i.eq(1)
  82             yield self.port.eq(data)
  83             yield self.count.eq(self.count + 1)
  84             yield
  85             yield self.go_i.eq(0)
  86             yield self.port.eq(0)
  87
  88     def send(self, data, delay):
  89         """
  90         Schedules the module to send some `data`, counting `delay` cycles after
  91         `rel_i` becomes active.
  92
  93         To be called from the main test-bench process,
  94         it returns in the same cycle.
  95
  96         Communication with the worker process is done by means of
  97         combinatorial simulation-only signals.
  98
  99         """
 100         yield self.data.eq(data)
 101         yield self.delay.eq(delay)
 102
 103
 104 class ResultConsumer:
 105     """
 106     Consumes a result when requested by the Computation Unit
 107     (`dut` parameter), using the `rel_o` / `go_i` handshake.
 108
 109     Attaches itself to the `dut` result indexed by `op_index`.
 110
 111     Has a programmable delay between the assertion of `rel_o` and the
 112     `go_i` pulse.
 113
 114     Data is retrieved only during the cycle in which `go_i` is active.
 115
 116     It adds itself as a passive process to the simulation (`sim` parameter).
 117     Since it is passive, it will not hang the simulation, and does not need a
 118     flag to terminate itself.
 119     """
 120     def __init__(self, sim, dut, op_index):
 121         self.count = Signal(8, name=f"dest{op_index + 1}_count")
 122         """ transaction counter"""
 123         # data and handshake signals from the DUT
 124         self.port = dut.dest[op_index]
 125         self.go_i = dut.wr.go_i[op_index]
 126         self.rel_o = dut.wr.rel_o[op_index]
 127         # transaction parameters, passed via signals
 128         self.delay = Signal(8)
 129         self.expected = Signal.like(self.port)
 130         # add ourselves to the simulation process list
 131         sim.add_sync_process(self._process)
 132
 133     def _process(self):
 134         yield Passive()
 135         while True:
 136             # Settle() is needed to give a quick response to
 137             # the zero delay case
 138             yield Settle()
 139             # wait for rel_o to become active
 140             while not (yield self.rel_o):
 141                 yield
 142                 yield Settle()
 143             # read the transaction parameters
 144             delay = (yield self.delay)
 145             expected = (yield self.expected)
 146             # wait for `delay` cycles
 147             for _ in range(delay):
 148                 yield
 149             # activate go_i for one cycle
 150             yield self.go_i.eq(1)
 151             yield self.count.eq(self.count + 1)
 152             yield
 153             # check received data against the expected value
 154             result = (yield self.port)
 155             assert result == expected,\
 156                 f"expected {expected}, received {result}"
 157             yield self.go_i.eq(0)
 158             yield self.port.eq(0)
 159
 160     def receive(self, expected, delay):
 161         """
 162         Schedules the module to receive some result,
 163         counting `delay` cycles after `rel_i` becomes active.
 164         As 'go_i' goes active, check the result with `expected`.
 165
 166         To be called from the main test-bench process,
 167         it returns in the same cycle.
 168
 169         Communication with the worker process is done by means of
 170         combinatorial simulation-only signals.
 171         """
 172         yield self.expected.eq(expected)
 173         yield self.delay.eq(delay)
 174
 175
 176 def op_sim(dut, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0):
 177     yield dut.issue_i.eq(0)
 178     yield
 179     yield dut.src_i[0].eq(a)
 180     yield dut.src_i[1].eq(b)
 181     yield dut.oper_i.insn_type.eq(op)
 182     yield dut.oper_i.invert_in.eq(inv_a)
 183     yield dut.oper_i.imm_data.data.eq(imm)
 184     yield dut.oper_i.imm_data.ok.eq(imm_ok)
 185     yield dut.oper_i.zero_a.eq(zero_a)
 186     yield dut.issue_i.eq(1)
 187     yield
 188     yield dut.issue_i.eq(0)
 189     yield
 190     if not imm_ok or not zero_a:
 191         yield dut.rd.go_i.eq(0b11)
 192         while True:
 193             yield
 194             rd_rel_o = yield dut.rd.rel_o
 195             print("rd_rel", rd_rel_o)
 196             if rd_rel_o:
 197                 break
 198         yield dut.rd.go_i.eq(0)
 199     else:
 200         print("no go rd")
 201
 202     if len(dut.src_i) == 3:
 203         yield dut.rd.go_i.eq(0b100)
 204         while True:
 205             yield
 206             rd_rel_o = yield dut.rd.rel_o
 207             print("rd_rel", rd_rel_o)
 208             if rd_rel_o:
 209                 break
 210         yield dut.rd.go_i.eq(0)
 211     else:
 212         print("no 3rd rd")
 213
 214     req_rel_o = yield dut.wr.rel_o
 215     result = yield dut.data_o
 216     print("req_rel", req_rel_o, result)
 217     while True:
 218         req_rel_o = yield dut.wr.rel_o
 219         result = yield dut.data_o
 220         print("req_rel", req_rel_o, result)
 221         if req_rel_o:
 222             break
 223         yield
 224     yield dut.wr.go_i[0].eq(1)
 225     yield Settle()
 226     result = yield dut.data_o
 227     yield
 228     print("result", result)
 229     yield dut.wr.go_i[0].eq(0)
 230     yield
 231     return result
 232
 233
 234 def scoreboard_sim_fsm(dut, producers, consumers):
 235
 236     # stores the operation count
 237     op_count = 0
 238
 239     def op_sim_fsm(a, b, direction, expected, delays):
 240         print("op_sim_fsm", a, b, direction, expected)
 241         yield dut.issue_i.eq(0)
 242         yield
 243         # forward data and delays to the producers and consumers
 244         yield from producers[0].send(a, delays[0])
 245         yield from producers[1].send(b, delays[1])
 246         yield from consumers[0].receive(expected, delays[2])
 247         # submit operation, and assert issue_i for one cycle
 248         yield dut.oper_i.sdir.eq(direction)
 249         yield dut.issue_i.eq(1)
 250         yield
 251         yield dut.issue_i.eq(0)
 252         # wait for busy to be negated
 253         yield Settle()
 254         while (yield dut.busy_o):
 255             yield
 256             yield Settle()
 257         # update the operation count
 258         nonlocal op_count
 259         op_count = (op_count + 1) & 255
 260         # check that producers and consumers have the same count
 261         # this assures that no data was left unused or was lost
 262         assert (yield producers[0].count) == op_count
 263         assert (yield producers[1].count) == op_count
 264         assert (yield consumers[0].count) == op_count
 265
 266     # 13 >> 2 = 3
 267     # operand 1 arrives immediately
 268     # operand 2 arrives after operand 1
 269     # write data is accepted immediately
 270     yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
 271     # 3 << 4 = 48
 272     # operand 2 arrives immediately
 273     # operand 1 arrives after operand 2
 274     # write data is accepted after some delay
 275     yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
 276     # 21 << 0 = 21
 277     # operands 1 and 2 arrive at the same time
 278     # write data is accepted after some delay
 279     yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
 280
 281
 282 def scoreboard_sim_dummy(op):
 283     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 284                         src_delays=[0, 2, 1], dest_delays=[0])
 285     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 286                         src_delays=[2, 1, 0], dest_delays=[2])
 287     # test all combinations of masked input ports
 288     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [0],
 289                         rdmaskn=[1, 0, 0],
 290                         src_delays=[0, 2, 1], dest_delays=[0])
 291     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 292                         rdmaskn=[0, 1, 0],
 293                         src_delays=[2, 1, 0], dest_delays=[2])
 294     yield from op.issue([5, 2, 0], MicrOp.OP_NOP, [5],
 295                         rdmaskn=[0, 0, 1],
 296                         src_delays=[2, 1, 0], dest_delays=[2])
 297     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [9],
 298                         rdmaskn=[0, 1, 1],
 299                         src_delays=[2, 1, 0], dest_delays=[2])
 300     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 301                         rdmaskn=[1, 1, 0],
 302                         src_delays=[2, 1, 0], dest_delays=[2])
 303     yield from op.issue([9, 2, 0], MicrOp.OP_NOP, [0],
 304                         rdmaskn=[1, 1, 1],
 305                         src_delays=[2, 1, 0], dest_delays=[2])
 306
 307
 308 class OpSim:
 309     """ALU Operation issuer
 310
 311     Issues operations to the DUT"""
 312     def __init__(self, dut, sim):
 313         self.op_count = 0
 314         self.zero_a_count = 0
 315         self.imm_ok_count = 0
 316         self.rdmaskn_count = [0] * len(dut.src_i)
 317         self.dut = dut
 318         # create one operand producer for each input port
 319         self.producers = list()
 320         for i in range(len(dut.src_i)):
 321             self.producers.append(OperandProducer(sim, dut, i))
 322         # create one result consumer for each output port
 323         self.consumers = list()
 324         for i in range(len(dut.dest)):
 325             self.consumers.append(ResultConsumer(sim, dut, i))
 326     def issue(self, src_i, op, expected, src_delays, dest_delays,
 327               inv_a=0, imm=0, imm_ok=0, zero_a=0, rdmaskn=None):
 328         """Executes the issue operation"""
 329         dut = self.dut
 330         producers = self.producers
 331         consumers = self.consumers
 332         if rdmaskn is None:
 333             rdmaskn = [0] * len(src_i)
 334         yield dut.issue_i.eq(0)
 335         yield
 336         # forward data and delays to the producers and consumers
 337         # first, send special cases (with zero_a and/or imm_ok)
 338         if not zero_a:
 339             yield from producers[0].send(src_i[0], src_delays[0])
 340         if not imm_ok:
 341             yield from producers[1].send(src_i[1], src_delays[1])
 342         # then, send the rest (if any)
 343         for i in range(2, len(producers)):
 344             yield from producers[i].send(src_i[i], src_delays[i])
 345         for i in range(len(consumers)):
 346             yield from consumers[i].receive(expected[i], dest_delays[i])
 347         # submit operation, and assert issue_i for one cycle
 348         yield dut.oper_i.insn_type.eq(op)
 349         if hasattr(dut.oper_i, "invert_in"):
 350             yield dut.oper_i.invert_in.eq(inv_a)
 351         if hasattr(dut.oper_i, "imm_data"):
 352             yield dut.oper_i.imm_data.data.eq(imm)
 353             yield dut.oper_i.imm_data.ok.eq(imm_ok)
 354         if hasattr(dut.oper_i, "zero_a"):
 355             yield dut.oper_i.zero_a.eq(zero_a)
 356         if hasattr(dut, "rdmaskn"):
 357             rdmaskn_bits = 0
 358             for i in range(len(rdmaskn)):
 359                 rdmaskn_bits |= rdmaskn[i] << i
 360             yield dut.rdmaskn.eq(rdmaskn_bits)
 361         yield dut.issue_i.eq(1)
 362         yield
 363         yield dut.issue_i.eq(0)
 364         # wait for busy to be negated
 365         yield Settle()
 366         while (yield dut.busy_o):
 367             yield
 368             yield Settle()
 369         # update the operation count
 370         self.op_count = (self.op_count + 1) & 255
 371         # On zero_a, imm_ok and rdmaskn executions, the producer counters will
 372         # fall behind. But, by summing the following counts, the invariant is
 373         # preserved.
 374         if zero_a and not rdmaskn[0]:
 375             self.zero_a_count = self.zero_a_count + 1
 376         if imm_ok and not rdmaskn[1]:
 377             self.imm_ok_count = self.imm_ok_count + 1
 378         for i in range(len(rdmaskn)):
 379             if rdmaskn[i]:
 380                 self.rdmaskn_count[i] = self.rdmaskn_count[i] + 1
 381         # check that producers and consumers have the same count
 382         # this assures that no data was left unused or was lost
 383         # first, check special cases (zero_a and imm_ok)
 384         port_a_cnt = \
 385             (yield producers[0].count) \
 386             + self.zero_a_count \
 387             + self.rdmaskn_count[0]
 388         port_b_cnt = \
 389             (yield producers[1].count) \
 390             + self.imm_ok_count \
 391             + self.rdmaskn_count[1]
 392         assert port_a_cnt == self.op_count
 393         assert port_b_cnt == self.op_count
 394         # then, check the rest (if any)
 395         for i in range(2, len(producers)):
 396             port_cnt = (yield producers[i].count) + self.rdmaskn_count[i]
 397             assert port_cnt == self.op_count
 398         # check write counter
 399         for i in range(len(consumers)):
 400             assert (yield consumers[i].count) == self.op_count
 401
 402
 403 def scoreboard_sim(op):
 404     # zero (no) input operands test
 405     # 0 + 8 = 8
 406     yield from op.issue([5, 2], MicrOp.OP_ADD, [8],
 407                         zero_a=1, imm=8, imm_ok=1,
 408                         src_delays=[0, 2], dest_delays=[0])
 409     # 5 + 8 = 13
 410     yield from op.issue([5, 2], MicrOp.OP_ADD, [13],
 411                         inv_a=0, imm=8, imm_ok=1,
 412                         src_delays=[2, 0], dest_delays=[2])
 413     # 5 + 2 = 7
 414     yield from op.issue([5, 2], MicrOp.OP_ADD, [7],
 415                         src_delays=[1, 1], dest_delays=[1])
 416     # (-6) + 2 = (-4)
 417     yield from op.issue([5, 2], MicrOp.OP_ADD, [65532],
 418                         inv_a=1,
 419                         src_delays=[1, 2], dest_delays=[0])
 420     # 0 + 2 = 2
 421     yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
 422                         zero_a=1,
 423                         src_delays=[2, 0], dest_delays=[1])
 424
 425     # test combinatorial zero-delay operation
 426     # In the test ALU, any operation other than ADD, MUL or SHR
 427     # is zero-delay, and do a subtraction.
 428     # 5 - 2 = 3
 429     yield from op.issue([5, 2], MicrOp.OP_NOP, [3],
 430                         src_delays=[0, 1], dest_delays=[2])
 431     # test all combinations of masked input ports
 432     # 5 + 0 (masked) = 5
 433     yield from op.issue([5, 2], MicrOp.OP_ADD, [5],
 434                         rdmaskn=[0, 1],
 435                         src_delays=[2, 1], dest_delays=[0])
 436     # 0 (masked) + 2 = 2
 437     yield from op.issue([5, 2], MicrOp.OP_ADD, [2],
 438                         rdmaskn=[1, 0],
 439                         src_delays=[1, 2], dest_delays=[1])
 440     # 0 (masked) + 0 (masked) = 0
 441     yield from op.issue([5, 2], MicrOp.OP_ADD, [0],
 442                         rdmaskn=[1, 1],
 443                         src_delays=[1, 2], dest_delays=[1])
 444
 445
 446 def test_compunit_fsm():
 447     style = {
 448         'in': {'color': 'orange'},
 449         'out': {'color': 'yellow'},
 450     }
 451     traces = [
 452         'clk',
 453         ('operation port', {'color': 'red'}, [
 454             'cu_issue_i', 'cu_busy_o',
 455             {'comment': 'operation'},
 456             'oper_i_None__sdir']),
 457         ('operand 1 port', 'in', [
 458             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 459             ('cu_rd__go_i[1:0]', {'bit': 1}),
 460             'src1_i[7:0]']),
 461         ('operand 2 port', 'in', [
 462             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 463             ('cu_rd__go_i[1:0]', {'bit': 0}),
 464             'src2_i[7:0]']),
 465         ('result port', 'out', [
 466             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
 467         ('alu', {'submodule': 'alu'}, [
 468             ('prev port', 'in', [
 469                 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
 470                 ({'submodule': 'p'},
 471                     ['p_valid_i', 'p_ready_o'])]),
 472             ('next port', 'out', [
 473                 'n_data_o[7:0]',
 474                 ({'submodule': 'n'},
 475                     ['n_valid_o', 'n_ready_i'])])]),
 476         ('debug', {'module': 'top'},
 477             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 478
 479     write_gtkw(
 480         "test_compunit_fsm1.gtkw",
 481         "test_compunit_fsm1.vcd",
 482         traces, style,
 483         module='top.cu'
 484     )
 485     m = Module()
 486     alu = Shifter(8)
 487     dut = MultiCompUnit(8, alu, CompFSMOpSubset)
 488     m.submodules.cu = dut
 489
 490     vl = rtlil.convert(dut, ports=dut.ports())
 491     with open("test_compunit_fsm1.il", "w") as f:
 492         f.write(vl)
 493
 494     sim = Simulator(m)
 495     sim.add_clock(1e-6)
 496
 497     # create one operand producer for each input port
 498     prod_a = OperandProducer(sim, dut, 0)
 499     prod_b = OperandProducer(sim, dut, 1)
 500     # create an result consumer for the output port
 501     cons = ResultConsumer(sim, dut, 0)
 502     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 503                                                  [prod_a, prod_b],
 504                                                  [cons])))
 505     sim_writer = sim.write_vcd('test_compunit_fsm1.vcd',
 506                                traces=[prod_a.count,
 507                                        prod_b.count,
 508                                        cons.count])
 509     with sim_writer:
 510         sim.run()
 511
 512
 513 def test_compunit():
 514
 515     m = Module()
 516     alu = ALU(16)
 517     dut = MultiCompUnit(16, alu, CompALUOpSubset)
 518     m.submodules.cu = dut
 519
 520     vl = rtlil.convert(dut, ports=dut.ports())
 521     with open("test_compunit1.il", "w") as f:
 522         f.write(vl)
 523
 524     sim = Simulator(m)
 525     sim.add_clock(1e-6)
 526
 527     # create an operation issuer
 528     op = OpSim(dut, sim)
 529     sim.add_sync_process(wrap(scoreboard_sim(op)))
 530     sim_writer = sim.write_vcd('test_compunit1.vcd')
 531     with sim_writer:
 532         sim.run()
 533
 534
 535 class CompUnitParallelTest:
 536     def __init__(self, dut):
 537         self.dut = dut
 538
 539         # Operation cycle should not take longer than this:
 540         self.MAX_BUSY_WAIT = 50
 541
 542         # Minimum duration in which issue_i will be kept inactive,
 543         # during which busy_o must remain low.
 544         self.MIN_BUSY_LOW = 5
 545
 546         # Number of cycles to stall until the assertion of go.
 547         # One value, for each port. Can be zero, for no delay.
 548         self.RD_GO_DELAY = [0, 3]
 549
 550         # store common data for the input operation of the processes
 551         # input operation:
 552         self.op = 0
 553         self.inv_a = self.zero_a = 0
 554         self.imm = self.imm_ok = 0
 555         self.imm_control = (0, 0)
 556         self.rdmaskn = (0, 0)
 557         # input data:
 558         self.operands = (0, 0)
 559
 560         # Indicates completion of the sub-processes
 561         self.rd_complete = [False, False]
 562
 563     def driver(self):
 564         print("Begin parallel test.")
 565         yield from self.operation(5, 2, MicrOp.OP_ADD)
 566
 567     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
 568                   rdmaskn=(0, 0)):
 569         # store data for the operation
 570         self.operands = (a, b)
 571         self.op = op
 572         self.inv_a = inv_a
 573         self.imm = imm
 574         self.imm_ok = imm_ok
 575         self.zero_a = zero_a
 576         self.imm_control = (zero_a, imm_ok)
 577         self.rdmaskn = rdmaskn
 578
 579         # Initialize completion flags
 580         self.rd_complete = [False, False]
 581
 582         # trigger operation cycle
 583         yield from self.issue()
 584
 585         # check that the sub-processes completed, before the busy_o cycle ended
 586         for completion in self.rd_complete:
 587             assert completion
 588
 589     def issue(self):
 590         # issue_i starts inactive
 591         yield self.dut.issue_i.eq(0)
 592
 593         for n in range(self.MIN_BUSY_LOW):
 594             yield
 595             # busy_o must remain inactive. It cannot rise on its own.
 596             busy_o = yield self.dut.busy_o
 597             assert not busy_o
 598
 599         # activate issue_i to begin the operation cycle
 600         yield self.dut.issue_i.eq(1)
 601
 602         # at the same time, present the operation
 603         yield self.dut.oper_i.insn_type.eq(self.op)
 604         yield self.dut.oper_i.invert_in.eq(self.inv_a)
 605         yield self.dut.oper_i.imm_data.data.eq(self.imm)
 606         yield self.dut.oper_i.imm_data.ok.eq(self.imm_ok)
 607         yield self.dut.oper_i.zero_a.eq(self.zero_a)
 608         rdmaskn = self.rdmaskn[0] | (self.rdmaskn[1] << 1)
 609         yield self.dut.rdmaskn.eq(rdmaskn)
 610
 611         # give one cycle for the CompUnit to latch the data
 612         yield
 613
 614         # busy_o must keep being low in this cycle, because issue_i was
 615         # low on the previous cycle.
 616         # It cannot rise on its own.
 617         # Also, busy_o and issue_i must never be active at the same time, ever.
 618         busy_o = yield self.dut.busy_o
 619         assert not busy_o
 620
 621         # Lower issue_i
 622         yield self.dut.issue_i.eq(0)
 623
 624         # deactivate inputs along with issue_i, so we can be sure the data
 625         # was latched at the correct cycle
 626         # note: rdmaskn must be held, while busy_o is active
 627         # TODO: deactivate rdmaskn when the busy_o cycle ends
 628         yield self.dut.oper_i.insn_type.eq(0)
 629         yield self.dut.oper_i.invert_in.eq(0)
 630         yield self.dut.oper_i.imm_data.data.eq(0)
 631         yield self.dut.oper_i.imm_data.ok.eq(0)
 632         yield self.dut.oper_i.zero_a.eq(0)
 633         yield
 634
 635         # wait for busy_o to lower
 636         # timeout after self.MAX_BUSY_WAIT cycles
 637         for n in range(self.MAX_BUSY_WAIT):
 638             # sample busy_o in the current cycle
 639             busy_o = yield self.dut.busy_o
 640             if not busy_o:
 641                 # operation cycle ends when busy_o becomes inactive
 642                 break
 643             yield
 644
 645         # if busy_o is still active, a timeout has occurred
 646         # TODO: Uncomment this, once the test is complete:
 647         # assert not busy_o
 648
 649         if busy_o:
 650             print("If you are reading this, "
 651                   "it's because the above test failed, as expected,\n"
 652                   "with a timeout. It must pass, once the test is complete.")
 653             return
 654
 655         print("If you are reading this, "
 656               "it's because the above test unexpectedly passed.")
 657
 658     def rd(self, rd_idx):
 659         # wait for issue_i to rise
 660         while True:
 661             issue_i = yield self.dut.issue_i
 662             if issue_i:
 663                 break
 664             # issue_i has not risen yet, so rd must keep low
 665             rel = yield self.dut.rd.rel_o[rd_idx]
 666             assert not rel
 667             yield
 668
 669         # we do not want rd to rise on an immediate operand
 670         # if it is immediate, exit the process
 671         # likewise, if the read mask is active
 672         # TODO: don't exit the process, monitor rd instead to ensure it
 673         #       doesn't rise on its own
 674         if self.rdmaskn[rd_idx] or self.imm_control[rd_idx]:
 675             self.rd_complete[rd_idx] = True
 676             return
 677
 678         # issue_i has risen. rel must rise on the next cycle
 679         rel = yield self.dut.rd.rel_o[rd_idx]
 680         assert not rel
 681
 682         # stall for additional cycles. Check that rel doesn't fall on its own
 683         for n in range(self.RD_GO_DELAY[rd_idx]):
 684             yield
 685             rel = yield self.dut.rd.rel_o[rd_idx]
 686             assert rel
 687
 688         # Before asserting "go", make sure "rel" has risen.
 689         # The use of Settle allows "go" to be set combinatorially,
 690         # rising on the same cycle as "rel".
 691         yield Settle()
 692         rel = yield self.dut.rd.rel_o[rd_idx]
 693         assert rel
 694
 695         # assert go for one cycle, passing along the operand value
 696         yield self.dut.rd.go_i[rd_idx].eq(1)
 697         yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
 698         # check that the operand was sent to the alu
 699         # TODO: Properly check the alu protocol
 700         yield Settle()
 701         alu_input = yield self.dut.get_in(rd_idx)
 702         assert alu_input == self.operands[rd_idx]
 703         yield
 704
 705         # rel must keep high, since go was inactive in the last cycle
 706         rel = yield self.dut.rd.rel_o[rd_idx]
 707         assert rel
 708
 709         # finish the go one-clock pulse
 710         yield self.dut.rd.go_i[rd_idx].eq(0)
 711         yield self.dut.src_i[rd_idx].eq(0)
 712         yield
 713
 714         # rel must have gone low in response to go being high
 715         # on the previous cycle
 716         rel = yield self.dut.rd.rel_o[rd_idx]
 717         assert not rel
 718
 719         self.rd_complete[rd_idx] = True
 720
 721         # TODO: check that rel doesn't rise again until the end of the
 722         #       busy_o cycle
 723
 724     def wr(self, wr_idx):
 725         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
 726         yield
 727         # TODO: also when dut.wr.go is set, check the output against the
 728         # self.expected_o and assert.  use dut.get_out(wr_idx) to do so.
 729
 730     def run_simulation(self, vcd_name):
 731         m = Module()
 732         m.submodules.cu = self.dut
 733         sim = Simulator(m)
 734         sim.add_clock(1e-6)
 735
 736         sim.add_sync_process(wrap(self.driver()))
 737         sim.add_sync_process(wrap(self.rd(0)))
 738         sim.add_sync_process(wrap(self.rd(1)))
 739         sim.add_sync_process(wrap(self.wr(0)))
 740         sim_writer = sim.write_vcd(vcd_name)
 741         with sim_writer:
 742             sim.run()
 743
 744
 745 def test_compunit_regspec2_fsm():
 746
 747     inspec = [('INT', 'data', '0:15'),
 748               ('INT', 'shift', '0:15')]
 749     outspec = [('INT', 'data', '0:15')]
 750
 751     regspec = (inspec, outspec)
 752
 753     m = Module()
 754     alu = Shifter(8)
 755     dut = MultiCompUnit(regspec, alu, CompFSMOpSubset)
 756     m.submodules.cu = dut
 757
 758     sim = Simulator(m)
 759     sim.add_clock(1e-6)
 760
 761     # create one operand producer for each input port
 762     prod_a = OperandProducer(sim, dut, 0)
 763     prod_b = OperandProducer(sim, dut, 1)
 764     # create an result consumer for the output port
 765     cons = ResultConsumer(sim, dut, 0)
 766     sim.add_sync_process(wrap(scoreboard_sim_fsm(dut,
 767                                                  [prod_a, prod_b],
 768                                                  [cons])))
 769     sim_writer = sim.write_vcd('test_compunit_regspec2_fsm.vcd',
 770                                traces=[prod_a.count,
 771                                        prod_b.count,
 772                                        cons.count])
 773     with sim_writer:
 774         sim.run()
 775
 776
 777 def test_compunit_regspec3():
 778
 779     style = {
 780         'in': {'color': 'orange'},
 781         'out': {'color': 'yellow'},
 782     }
 783     traces = [
 784         'clk',
 785         ('operation port', {'color': 'red'}, [
 786             'cu_issue_i', 'cu_busy_o',
 787             {'comment': 'operation'},
 788             ('oper_i_None__insn_type'
 789              + ('' if is_engine_pysim() else '[6:0]'),
 790              {'display': 'insn_type'})]),
 791         ('operand 1 port', 'in', [
 792             ('cu_rd__rel_o[2:0]', {'bit': 2}),
 793             ('cu_rd__go_i[2:0]', {'bit': 2}),
 794             'src1_i[15:0]']),
 795         ('operand 2 port', 'in', [
 796             ('cu_rd__rel_o[2:0]', {'bit': 1}),
 797             ('cu_rd__go_i[2:0]', {'bit': 1}),
 798             'src2_i[15:0]']),
 799         ('operand 3 port', 'in', [
 800             ('cu_rd__rel_o[2:0]', {'bit': 0}),
 801             ('cu_rd__go_i[2:0]', {'bit': 0}),
 802             'src1_i[15:0]']),
 803         ('result port', 'out', [
 804             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 805         ('alu', {'submodule': 'alu'}, [
 806             ('prev port', 'in', [
 807                 'oper_i_None__insn_type', 'i1[15:0]',
 808                 'valid_i', 'ready_o']),
 809             ('next port', 'out', [
 810                 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
 811
 812     write_gtkw("test_compunit_regspec3.gtkw",
 813                "test_compunit_regspec3.vcd",
 814                traces, style,
 815                clk_period=1e-6,
 816                module='top.cu')
 817
 818     inspec = [('INT', 'a', '0:15'),
 819               ('INT', 'b', '0:15'),
 820               ('INT', 'c', '0:15')]
 821     outspec = [('INT', 'o', '0:15')]
 822
 823     regspec = (inspec, outspec)
 824
 825     m = Module()
 826     alu = DummyALU(16)
 827     dut = MultiCompUnit(regspec, alu, CompCROpSubset)
 828     m.submodules.cu = dut
 829
 830     sim = Simulator(m)
 831     sim.add_clock(1e-6)
 832
 833     # create an operation issuer
 834     op = OpSim(dut, sim)
 835     sim.add_sync_process(wrap(scoreboard_sim_dummy(op)))
 836     sim_writer = sim.write_vcd('test_compunit_regspec3.vcd')
 837     with sim_writer:
 838         sim.run()
 839
 840
 841 def test_compunit_regspec1():
 842
 843     style = {
 844         'in': {'color': 'orange'},
 845         'out': {'color': 'yellow'},
 846     }
 847     traces = [
 848         'clk',
 849         ('operation port', {'color': 'red'}, [
 850             'cu_issue_i', 'cu_busy_o',
 851             {'comment': 'operation'},
 852             ('oper_i_None__insn_type'
 853              + ('' if is_engine_pysim() else '[6:0]'),
 854              {'display': 'insn_type'}),
 855             ('oper_i_None__invert_in', {'display': 'invert_in'}),
 856             ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
 857             ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
 858             ('oper_i_None__zero_a', {'display': 'zero_a'})]),
 859         ('operand 1 port', 'in', [
 860             ('cu_rd__rel_o[1:0]', {'bit': 1}),
 861             ('cu_rd__go_i[1:0]', {'bit': 1}),
 862             'src1_i[15:0]']),
 863         ('operand 2 port', 'in', [
 864             ('cu_rd__rel_o[1:0]', {'bit': 0}),
 865             ('cu_rd__go_i[1:0]', {'bit': 0}),
 866             'src2_i[15:0]']),
 867         ('result port', 'out', [
 868             'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
 869         ('alu', {'submodule': 'alu'}, [
 870             ('prev port', 'in', [
 871                 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
 872                 'valid_i', 'ready_o']),
 873             ('next port', 'out', [
 874                 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
 875         ('debug', {'module': 'top'},
 876             ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
 877
 878     write_gtkw("test_compunit_regspec1.gtkw",
 879                "test_compunit_regspec1.vcd",
 880                traces, style,
 881                clk_period=1e-6,
 882                module='top.cu')
 883
 884     inspec = [('INT', 'a', '0:15'),
 885               ('INT', 'b', '0:15')]
 886     outspec = [('INT', 'o', '0:15')]
 887
 888     regspec = (inspec, outspec)
 889
 890     m = Module()
 891     alu = ALU(16)
 892     dut = MultiCompUnit(regspec, alu, CompALUOpSubset)
 893     m.submodules.cu = dut
 894
 895     vl = rtlil.convert(dut, ports=dut.ports())
 896     with open("test_compunit_regspec1.il", "w") as f:
 897         f.write(vl)
 898
 899     sim = Simulator(m)
 900     sim.add_clock(1e-6)
 901
 902     # create an operation issuer
 903     op = OpSim(dut, sim)
 904     sim.add_sync_process(wrap(scoreboard_sim(op)))
 905     sim_writer = sim.write_vcd('test_compunit_regspec1.vcd',
 906                                traces=[op.producers[0].count,
 907                                        op.producers[1].count,
 908                                        op.consumers[0].count])
 909     with sim_writer:
 910         sim.run()
 911
 912     test = CompUnitParallelTest(dut)
 913     test.run_simulation("test_compunit_parallel.vcd")
 914
 915
 916 if __name__ == '__main__':
 917     test_compunit()
 918     test_compunit_fsm()
 919     test_compunit_regspec1()
 920     test_compunit_regspec2_fsm()
 921     test_compunit_regspec3()