src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from soc.fu.regspec import RegSpecAPI
  12
  13 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  14 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  15 from openpower.decoder.power_decoder2 import Data
  16 from openpower.consts import MSR
  17
  18 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  19 from soc.experiment.l0_cache import PortInterface
  20 from soc.experiment.pimem import LDSTException
  21 from soc.experiment.compldst_multi import LDSTCompUnit
  22 from soc.config.test.test_loadstore import TestMemPspec
  23
  24 from soc.experiment.mmu import MMU
  25
  26 ########################################
  27
  28 def dcbz(dut, src1, src2, src3, imm, imm_ok=True, update=False,
  29           byterev=True):
  30     print("DCBZ", src1, src2, src3, imm, imm_ok, update)
  31     yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ)
  32     yield dut.oper_i.data_len.eq(2)  # half-word
  33     yield dut.oper_i.byte_reverse.eq(byterev)
  34     yield dut.src1_i.eq(src1)
  35     yield dut.src2_i.eq(src2)
  36     yield dut.src3_i.eq(src3)
  37     yield dut.oper_i.imm_data.data.eq(imm)
  38     yield dut.oper_i.imm_data.ok.eq(imm_ok)
  39     #FIXME: -- yield dut.oper_i.update.eq(update)
  40     yield dut.issue_i.eq(1)
  41     yield
  42     yield dut.issue_i.eq(0)
  43
  44     if imm_ok:
  45         active_rel = 0b101
  46     else:
  47         active_rel = 0b111
  48      # wait for all active rel signals to come up
  49     # guess: bug is here
  50     #while True:
  51     #    rel = yield dut.rd.rel_o
  52     #    if rel == active_rel:
  53     #        break
  54     #    yield
  55     #yield dut.rd.go_i.eq(active_rel)
  56     #yield
  57     #yield dut.rd.go_i.eq(0)
  58
  59     #yield from wait_for(dut.adr_rel_o, False, test1st=True)
  60     # yield from wait_for(dut.adr_rel_o)
  61     # yield dut.ad.go.eq(1)
  62     # yield
  63     # yield dut.ad.go.eq(0)
  64
  65     #if update:
  66     #    yield from wait_for(dut.wr.rel_o[1])
  67     #    yield dut.wr.go.eq(0b10)
  68     #    yield
  69     #    addr = yield dut.addr_o
  70     #    print("addr", addr)
  71     #    yield dut.wr.go.eq(0)
  72     #else:
  73     #    addr = None
  74
  75     # commented out for debugging
  76     #yield from wait_for(dut.sto_rel_o)
  77     #yield dut.go_st_i.eq(1)
  78     #yield
  79     #yield dut.go_st_i.eq(0)
  80     #yield from wait_for(dut.busy_o, False)
  81     # wait_for(dut.stwd_mem_o)
  82     #yield
  83     #return addr
  84
  85
  86 def ldst_sim(dut):
  87     yield from dcbz(dut, 4, 0, 3, 2) # FIXME
  88     yield
  89
  90 ########################################
  91
  92
  93 class TestLDSTCompUnitMMU(LDSTCompUnit):
  94
  95     def __init__(self, rwid, pspec):
  96         from soc.experiment.l0_cache import TstL0CacheBuffer
  97         self.l0 = l0 = TstL0CacheBuffer(pspec)
  98         pi = l0.l0.dports[0]
  99         LDSTCompUnit.__init__(self, pi, rwid, 4)
 100
 101     def elaborate(self, platform):
 102         m = LDSTCompUnit.elaborate(self, platform)
 103         m.submodules.l0 = self.l0
 104         # link addr-go direct to rel
 105         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 106         return m
 107
 108
 109 def test_scoreboard_mmu():
 110
 111     units = {}
 112     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 113                          imem_ifacetype='bare_wb',
 114                          addr_wid=48,
 115                          mask_wid=8,
 116                          reg_wid=64,
 117                          units=units)
 118
 119     dut = TestLDSTCompUnitMMU(16,pspec)
 120     vl = rtlil.convert(dut, ports=dut.ports())
 121     with open("test_ldst_comp_mmu1.il", "w") as f:
 122         f.write(vl)
 123
 124     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 125
 126 ########################################
 127 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
 128
 129     def __init__(self, pspec):
 130         from soc.experiment.l0_cache import TstL0CacheBuffer
 131         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 132         regspec = LDSTPipeSpec.regspec
 133         self.l0 = l0 = TstL0CacheBuffer(pspec)
 134         self.mmu = MMU()
 135         pi = l0.l0.dports[0]
 136         LDSTCompUnit.__init__(self, pi, regspec, 4)
 137
 138     def elaborate(self, platform):
 139         m = LDSTCompUnit.elaborate(self, platform)
 140         m.submodules.l0 = self.l0
 141         m.submodules.mmu = self.mmu
 142         # link addr-go direct to rel
 143         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 144
 145         # link mmu and dcache together
 146         dcache = self.l0.pimem.dcache
 147         mmu = self.mmu
 148         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 149         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 150
 151
 152         return m
 153
 154
 155 def test_scoreboard_regspec_mmu():
 156
 157     units = {}
 158     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 159                          imem_ifacetype='bare_wb',
 160                          addr_wid=48,
 161                          mask_wid=8,
 162                          reg_wid=64,
 163                          units=units)
 164
 165     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 166
 167     # TODO: setup pagetables for MMU
 168
 169     vl = rtlil.convert(dut, ports=dut.ports())
 170     with open("test_ldst_comp_mmu2.il", "w") as f:
 171         f.write(vl)
 172
 173     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 174
 175
 176 if __name__ == '__main__':
 177     test_scoreboard_regspec_mmu()
 178     #only one test for now -- test_scoreboard_mmu()