src/soc/experiment/test/test_dcbz_pi.py

   1 """DCache PortInterface Test
   2     starting as a copy to test_ldst_pi.py
   3 """
   4
   5 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   6 from nmigen.cli import main
   7 from nmigen.cli import rtlil
   8 from nmutil.mask import Mask, masked
   9 from nmutil.util import Display
  10 from random import randint, seed
  11
  12 if True:
  13     from nmigen.back.pysim import Simulator, Delay, Settle
  14 else:
  15     from nmigen.sim.cxxsim import Simulator, Delay, Settle
  16 from nmutil.util import wrap
  17
  18 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst, pi_dcbz
  19 from soc.config.test.test_loadstore import TestMemPspec
  20 from soc.config.loadstore import ConfigMemoryPortInterface
  21
  22 from soc.fu.ldst.loadstore import LoadStore1
  23 from soc.experiment.mmu import MMU
  24
  25 from nmigen.compat.sim import run_simulation
  26
  27
  28 stop = False
  29
  30 def b(x): # byte-reverse function
  31     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  32                           byteorder='big', signed=False)
  33
  34 def wb_get(wb, mem):
  35     """simulator process for getting memory load requests
  36     """
  37
  38     global stop
  39     assert(stop==False)
  40
  41     while not stop:
  42         while True: # wait for dc_valid
  43             if stop:
  44                 return
  45             cyc = yield (wb.cyc)
  46             stb = yield (wb.stb)
  47             if cyc and stb:
  48                 break
  49             yield
  50         addr = (yield wb.adr) << 3
  51         if addr not in mem:
  52             print ("    WB LOOKUP NO entry @ %x, returning zero" % (addr))
  53
  54         # read or write?
  55         we = (yield wb.we)
  56         if we:
  57             store = (yield wb.dat_w)
  58             sel = (yield wb.sel)
  59             data = mem.get(addr, 0)
  60             # note we assume 8-bit sel, here
  61             res = 0
  62             for i in range(8):
  63                 mask = 0xff << (i*8)
  64                 if sel & (1<<i):
  65                     res |= store & mask
  66                 else:
  67                     res |= data & mask
  68             mem[addr] = res
  69             print ("    DCACHE set %x mask %x data %x" % (addr, sel, res))
  70         else:
  71             data = mem.get(addr, 0)
  72             yield wb.dat_r.eq(data)
  73             print ("    DCACHE get %x data %x" % (addr, data))
  74
  75         yield wb.ack.eq(1)
  76         yield
  77         yield wb.ack.eq(0)
  78         yield
  79
  80 def setup_mmu():
  81
  82     global stop
  83     stop = False
  84
  85     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  86                          imem_ifacetype='',
  87                          addr_wid=48,
  88                          #disable_cache=True, # hmmm...
  89                          mask_wid=8,
  90                          reg_wid=64)
  91
  92     m = Module()
  93     comb = m.d.comb
  94     cmpi = ConfigMemoryPortInterface(pspec)
  95     m.submodules.ldst = ldst = cmpi.pi
  96     m.submodules.mmu = mmu = MMU()
  97     dcache = ldst.dcache
  98
  99     l_in, l_out = mmu.l_in, mmu.l_out
 100     d_in, d_out = dcache.d_in, dcache.d_out
 101     wb_out, wb_in = dcache.wb_out, dcache.wb_in
 102
 103     # link mmu and dcache together
 104     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 105     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 106
 107     # link ldst and MMU together
 108     comb += l_in.eq(ldst.m_out)
 109     comb += ldst.m_in.eq(l_out)
 110
 111     return m, cmpi
 112
 113 ### test case for dcbz
 114
 115 def _test_dcbz_addr_zero(dut, mem):
 116     mmu = dut.submodules.mmu
 117     pi = dut.submodules.ldst.pi
 118     global stop
 119     stop = False
 120
 121     yield mmu.rin.prtbl.eq(0x1000000) # set process table
 122     yield
 123
 124     addr = 0x100e0
 125     data = 0xf553b658ba7e1f51
 126
 127     yield from pi_st(pi, addr, data, 8, msr_pr=0)
 128     yield
 129
 130     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 131     assert ld_data == 0xf553b658ba7e1f51
 132     ld_data = yield from pi_ld(pi, addr, 8, msr_pr=0)
 133     assert ld_data == 0xf553b658ba7e1f51
 134
 135     ## verify this one first
 136     ## is_dcbz 1 ## addrok 1
 137     ##print("do_dcbz ===============")
 138     ##yield from pi_dcbz(pi, addr, msr_pr=0)
 139     ##yield
 140
 141     yield
 142     stop = True
 143
 144 #FIXME: rename
 145 def test_dcbz_addr_zero():
 146
 147     m, cmpi = setup_mmu()
 148
 149     mem = {
 150            0x10000:    # PARTITION_TABLE_2
 151                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
 152            b(0x800000000100000b),
 153
 154            0x30000:     # RADIX_ROOT_PTE
 155                         # V = 1 L = 0 NLB = 0x400 NLS = 9
 156            b(0x8000000000040009),
 157
 158            0x40000:     # RADIX_SECOND_LEVEL
 159                         # V = 1 L = 1 SW = 0 RPN = 0
 160                         # R = 1 C = 1 ATT = 0 EAA 0x7
 161            b(0xc000000000000183),
 162
 163            0x1000000:   # PROCESS_TABLE_3
 164                         # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
 165            b(0x40000000000300ad),
 166
 167            0x10004: 0
 168
 169     }
 170
 171     # nmigen Simulation
 172     sim = Simulator(m)
 173     sim.add_clock(1e-6)
 174
 175     sim.add_sync_process(wrap(_test_dcbz_addr_zero(m, mem)))
 176     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 177     with sim.write_vcd('test_dcbz_addr_zero.vcd'):
 178         sim.run()
 179
 180 if __name__ == '__main__':
 181     test_dcbz_addr_zero()