src/soc/experiment/testmem.py

   1 from nmigen import Module, Elaboratable, Memory
   2
   3
   4 class TestMemory(Elaboratable):
   5     def __init__(self, regwid, addrw, granularity=None):
   6         self.ddepth = 1 # regwid //8
   7         depth = (1<<addrw) // self.ddepth
   8         self.depth = depth
   9         self.regwid = regwid
  10         self.mem   = Memory(width=regwid, depth=depth,
  11                             init=range(0, depth*2, 2))
  12         self.rdport = self.mem.read_port() # not now transparent=False)
  13         self.wrport = self.mem.write_port(granularity=granularity)
  14
  15     def elaborate(self, platform):
  16         m = Module()
  17         m.submodules.rdport = self.rdport
  18         m.submodules.wrport = self.wrport
  19         return m
  20
  21     def __iter__(self):
  22         yield self.rdport.addr
  23         yield self.rdport.data
  24         yield self.rdport.en
  25         yield self.wrport.addr
  26         yield self.wrport.data
  27         yield self.wrport.en
  28
  29     def ports(self):
  30         return list(self)