start putting state info into LoadStore1, slowly putting loadstore1.vhdl
[soc.git] / src / soc / fu / alu / pipeline.py
1 from nmutil.singlepipe import ControlBase
2 from nmutil.pipemodbase import PipeModBaseChain
3 from soc.fu.alu.input_stage import ALUInputStage
4 from soc.fu.alu.main_stage import ALUMainStage
5 from soc.fu.alu.output_stage import ALUOutputStage
6
7 class ALUStages(PipeModBaseChain):
8 def get_chain(self):
9 inp = ALUInputStage(self.pspec)
10 main = ALUMainStage(self.pspec)
11 return [inp, main]
12
13
14 class ALUStageEnd(PipeModBaseChain):
15 def get_chain(self):
16 out = ALUOutputStage(self.pspec)
17 return [out]
18
19
20 class ALUBasePipe(ControlBase):
21 def __init__(self, pspec):
22 ControlBase.__init__(self)
23 self.pspec = pspec
24 self.pipe1 = ALUStages(pspec)
25 self.pipe2 = ALUStageEnd(pspec)
26 self._eqs = self.connect([self.pipe1, self.pipe2])
27
28 def elaborate(self, platform):
29 m = ControlBase.elaborate(self, platform)
30 m.submodules.pipe1 = self.pipe1
31 m.submodules.pipe2 = self.pipe2
32 m.d.comb += self._eqs
33 return m