2 from soc
.fu
.alu
.pipe_data
import ALUPipeSpec
3 from soc
.fu
.alu
.pipeline
import ALUBasePipe
4 from soc
.fu
.test
.common
import (TestCase
, TestAccumulatorBase
, ALUHelpers
)
5 from soc
.config
.endian
import bigendian
6 from soc
.decoder
.isa
.all
import ISA
7 from soc
.simulator
.program
import Program
8 from soc
.decoder
.selectable_int
import SelectableInt
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, MicrOp
, CryIn
)
10 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
11 from soc
.decoder
.power_decoder
import (create_pdecode
)
12 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
14 from nmigen
.cli
import rtlil
15 from nmutil
.formaltest
import FHDLTestCase
16 from nmigen
import Module
, Signal
18 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
19 # Also, check out the cxxsim nmigen branch, and latest yosys from git
20 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
23 def get_cu_inputs(dec2
, sim
):
24 """naming (res) must conform to ALUFunctionUnit input regspec
28 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
29 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
30 yield from ALUHelpers
.get_rd_sim_xer_ca(res
, sim
, dec2
) # XER.ca
31 yield from ALUHelpers
.get_sim_xer_so(res
, sim
, dec2
) # XER.so
33 print("alu get_cu_inputs", res
)
38 def set_alu_inputs(alu
, dec2
, sim
):
39 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
40 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
41 # and place it into data_i.b
43 inp
= yield from get_cu_inputs(dec2
, sim
)
44 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
45 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
47 yield from ALUHelpers
.set_xer_ca(alu
, dec2
, inp
)
48 yield from ALUHelpers
.set_xer_so(alu
, dec2
, inp
)
51 class ALUTestCase(TestAccumulatorBase
):
53 def case_1_regression(self
):
55 initial_regs
= [0] * 32
56 initial_regs
[1] = 0xb6a1fc6c8576af91
57 self
.add_case(Program(lst
, bigendian
), initial_regs
)
58 lst
= [f
"subf 3, 1, 2"]
59 initial_regs
= [0] * 32
60 initial_regs
[1] = 0x3d7f3f7ca24bac7b
61 initial_regs
[2] = 0xf6b2ac5e13ee15c2
62 self
.add_case(Program(lst
, bigendian
), initial_regs
)
63 lst
= [f
"subf 3, 1, 2"]
64 initial_regs
= [0] * 32
65 initial_regs
[1] = 0x833652d96c7c0058
66 initial_regs
[2] = 0x1c27ecff8a086c1a
67 self
.add_case(Program(lst
, bigendian
), initial_regs
)
69 initial_regs
= [0] * 32
70 initial_regs
[1] = 0x7f9497aaff900ea0
71 self
.add_case(Program(lst
, bigendian
), initial_regs
)
72 lst
= [f
"add. 3, 1, 2"]
73 initial_regs
= [0] * 32
74 initial_regs
[1] = 0xc523e996a8ff6215
75 initial_regs
[2] = 0xe1e5b9cc9864c4a8
76 self
.add_case(Program(lst
, bigendian
), initial_regs
)
77 lst
= [f
"add 3, 1, 2"]
78 initial_regs
= [0] * 32
79 initial_regs
[1] = 0x2e08ae202742baf8
80 initial_regs
[2] = 0x86c43ece9efe5baa
81 self
.add_case(Program(lst
, bigendian
), initial_regs
)
84 insns
= ["add", "add.", "subf"]
86 choice
= random
.choice(insns
)
87 lst
= [f
"{choice} 3, 1, 2"]
88 initial_regs
= [0] * 32
89 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
90 initial_regs
[2] = random
.randint(0, (1 << 64)-1)
91 self
.add_case(Program(lst
, bigendian
), initial_regs
)
93 def case_addme_ca_0(self
):
94 insns
= ["addme", "addme.", "addmeo", "addmeo."]
96 lst
= [f
"{choice} 6, 16"]
97 for value
in [0x7ffffffff,
99 initial_regs
= [0] * 32
100 initial_regs
[16] = value
102 xer
= SelectableInt(0, 64)
103 xer
[XER_bits
['CA']] = 0
104 initial_sprs
[special_sprs
['XER']] = xer
105 self
.add_case(Program(lst
, bigendian
),
106 initial_regs
, initial_sprs
)
108 def case_addme_ca_1(self
):
109 insns
= ["addme", "addme.", "addmeo", "addmeo."]
111 lst
= [f
"{choice} 6, 16"]
112 for value
in [0x7ffffffff, # fails, bug #476
114 initial_regs
= [0] * 32
115 initial_regs
[16] = value
117 xer
= SelectableInt(0, 64)
118 xer
[XER_bits
['CA']] = 1
119 initial_sprs
[special_sprs
['XER']] = xer
120 self
.add_case(Program(lst
, bigendian
),
121 initial_regs
, initial_sprs
)
123 def case_addme_ca_so_3(self
):
124 """bug where SO does not get passed through to CR0
126 lst
= ["addme. 6, 16"]
127 initial_regs
= [0] * 32
128 initial_regs
[16] = 0x7ffffffff
130 xer
= SelectableInt(0, 64)
131 xer
[XER_bits
['CA']] = 1
132 xer
[XER_bits
['SO']] = 1
133 initial_sprs
[special_sprs
['XER']] = xer
134 self
.add_case(Program(lst
, bigendian
),
135 initial_regs
, initial_sprs
)
137 def case_addze(self
):
138 insns
= ["addze", "addze.", "addzeo", "addzeo."]
140 lst
= [f
"{choice} 6, 16"]
141 initial_regs
= [0] * 32
142 initial_regs
[16] = 0x00ff00ff00ff0080
143 self
.add_case(Program(lst
, bigendian
), initial_regs
)
145 self
.add_case(Program(lst
, bigendian
), initial_regs
)
147 def case_addis_nonzero_r0_regression(self
):
148 lst
= [f
"addis 3, 0, 1"]
150 initial_regs
= [0] * 32
152 self
.add_case(Program(lst
, bigendian
), initial_regs
)
154 def case_addis_nonzero_r0(self
):
156 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
157 lst
= [f
"addis 3, 0, {imm}"]
159 initial_regs
= [0] * 32
160 initial_regs
[0] = random
.randint(0, (1 << 64)-1)
161 self
.add_case(Program(lst
, bigendian
), initial_regs
)
163 def case_rand_imm(self
):
164 insns
= ["addi", "addis", "subfic"]
166 choice
= random
.choice(insns
)
167 imm
= random
.randint(-(1 << 15), (1 << 15)-1)
168 lst
= [f
"{choice} 3, 1, {imm}"]
170 initial_regs
= [0] * 32
171 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
172 self
.add_case(Program(lst
, bigendian
), initial_regs
)
174 def case_0_adde(self
):
175 lst
= ["adde. 5, 6, 7"]
177 initial_regs
= [0] * 32
178 initial_regs
[6] = random
.randint(0, (1 << 64)-1)
179 initial_regs
[7] = random
.randint(0, (1 << 64)-1)
181 xer
= SelectableInt(0, 64)
182 xer
[XER_bits
['CA']] = 1
183 initial_sprs
[special_sprs
['XER']] = xer
184 self
.add_case(Program(lst
, bigendian
),
185 initial_regs
, initial_sprs
)
188 lst
= ["subf. 1, 6, 7",
190 initial_regs
= [0] * 32
191 initial_regs
[6] = 0x10
192 initial_regs
[7] = 0x05
193 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
196 lst
= ["cmp cr2, 0, 2, 3"]
197 initial_regs
= [0] * 32
198 initial_regs
[2] = 0xffffffffaaaaaaaa
199 initial_regs
[3] = 0x00000000aaaaaaaa
200 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
202 lst
= ["cmp cr2, 0, 4, 5"]
203 initial_regs
= [0] * 32
204 initial_regs
[4] = 0x00000000aaaaaaaa
205 initial_regs
[5] = 0xffffffffaaaaaaaa
206 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
209 lst
= ["cmp cr2, 1, 2, 3"]
210 initial_regs
= [0] * 32
211 initial_regs
[2] = 0xffffffffaaaaaaaa
212 initial_regs
[3] = 0x00000000aaaaaaaa
213 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
215 lst
= ["cmp cr2, 1, 4, 5"]
216 initial_regs
= [0] * 32
217 initial_regs
[4] = 0x00000000aaaaaaaa
218 initial_regs
[5] = 0xffffffffaaaaaaaa
219 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
221 def case_cmpl_microwatt_0(self
):
223 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
224 register_file.vhdl: Reading GPR 11 000000000001C026
225 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
226 cr_file.vhdl: Reading CR 35055050
227 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
230 lst
= ["cmpl 6, 0, 17, 10"]
231 initial_regs
= [0] * 32
232 initial_regs
[0x11] = 0x1c026
233 initial_regs
[0xa] = 0xFEDF3FFF0001C025
237 self
.add_case(Program(lst
, bigendian
), initial_regs
,
238 initial_sprs
= {'XER': XER
},
241 def case_cmpl_microwatt_0_disasm(self
):
242 """microwatt 1.bin: disassembled version
243 115b8: 40 50 d1 7c .long 0x7cd15040 # cmpl 6, 0, 17, 10
244 register_file.vhdl: Reading GPR 11 000000000001C026
245 register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
246 cr_file.vhdl: Reading CR 35055050
247 cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
250 dis
= ["cmpl 6, 0, 17, 10"]
251 lst
= bytes([0x40, 0x50, 0xd1, 0x7c]) # 0x7cd15040
252 initial_regs
= [0] * 32
253 initial_regs
[0x11] = 0x1c026
254 initial_regs
[0xa] = 0xFEDF3FFF0001C025
258 p
= Program(lst
, bigendian
)
259 p
.assembly
= '\n'.join(dis
)+'\n'
260 self
.add_case(p
, initial_regs
,
261 initial_sprs
= {'XER': XER
},
264 def case_cmplw_microwatt_1(self
):
266 10d94: 40 20 96 7c cmplw cr1,r22,r4
267 gpr: 00000000ffff6dc1 <- r4
268 gpr: 0000000000000000 <- r22
271 lst
= ["cmpl 1, 0, 22, 4"]
272 initial_regs
= [0] * 32
273 initial_regs
[4] = 0xffff6dc1
278 self
.add_case(Program(lst
, bigendian
), initial_regs
,
279 initial_sprs
= {'XER': XER
},
282 def case_cmpli_microwatt(self
):
283 """microwatt 1.bin: cmpli
284 123ac: 9c 79 8d 2a cmpli cr5,0,r13,31132
285 gpr: 00000000301fc7a7 <- r13
286 cr : 0000000090215393
287 xer: so 1 ca 0 32 0 ov 0 32 0
291 lst
= ["cmpli 5, 0, 13, 31132"]
292 initial_regs
= [0] * 32
293 initial_regs
[13] = 0x301fc7a7
297 self
.add_case(Program(lst
, bigendian
), initial_regs
,
298 initial_sprs
= {'XER': XER
},
301 def case_extsb(self
):
302 insns
= ["extsb", "extsh", "extsw"]
304 choice
= random
.choice(insns
)
305 lst
= [f
"{choice} 3, 1"]
307 initial_regs
= [0] * 32
308 initial_regs
[1] = random
.randint(0, (1 << 64)-1)
309 self
.add_case(Program(lst
, bigendian
), initial_regs
)
311 def case_cmpeqb(self
):
312 lst
= ["cmpeqb cr1, 1, 2"]
314 initial_regs
= [0] * 32
316 initial_regs
[2] = 0x0001030507090b0f
317 self
.add_case(Program(lst
, bigendian
), initial_regs
, {})
319 def case_ilang(self
):
320 pspec
= ALUPipeSpec(id_wid
=2)
321 alu
= ALUBasePipe(pspec
)
322 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
323 with
open("alu_pipeline.il", "w") as f
:
327 class TestRunner(unittest
.TestCase
):
329 def execute(self
, alu
,instruction
, pdecode2
, test
):
330 program
= test
.program
331 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
334 gen
= program
.generate_instructions()
335 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
337 index
= sim
.pc
.CIA
.value
//4
338 while index
< len(instructions
):
339 ins
, code
= instructions
[index
]
341 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
344 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
345 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
346 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
347 print("before: so/ov/32", so
, ov
, ov32
)
349 # ask the decoder to decode this binary data (endian'd)
351 yield pdecode2
.dec
.bigendian
.eq(bigendian
)
352 yield instruction
.eq(ins
) # raw binary instr.
354 fn_unit
= yield pdecode2
.e
.do
.fn_unit
355 asmcode
= yield pdecode2
.e
.asmcode
356 dec_asmcode
= yield pdecode2
.dec
.op
.asmcode
357 print ("asmcode", asmcode
, dec_asmcode
)
358 self
.assertEqual(fn_unit
, Function
.ALU
.value
)
359 yield from set_alu_inputs(alu
, pdecode2
, sim
)
361 # set valid for one cycle, propagate through pipeline...
362 yield alu
.p
.valid_i
.eq(1)
364 yield alu
.p
.valid_i
.eq(0)
366 opname
= code
.split(' ')[0]
367 yield from sim
.call(opname
)
368 index
= sim
.pc
.CIA
.value
//4
370 vld
= yield alu
.n
.valid_o
373 vld
= yield alu
.n
.valid_o
376 yield from self
.check_alu_outputs(alu
, pdecode2
, sim
, code
)
380 test_data
= ALUTestCase().test_data
383 instruction
= Signal(32)
386 opkls
= ALUPipeSpec
.opsubsetkls
388 pdecode
= create_pdecode()
389 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
, opkls
, fn_name
)
390 pdecode
= pdecode2
.dec
392 pspec
= ALUPipeSpec(id_wid
=2)
393 m
.submodules
.alu
= alu
= ALUBasePipe(pspec
)
395 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.do
)
396 comb
+= alu
.n
.ready_i
.eq(1)
397 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
403 for test
in test_data
:
405 program
= test
.program
406 with self
.subTest(test
.name
):
407 yield from self
.execute(alu
, instruction
, pdecode2
, test
)
409 sim
.add_sync_process(process
)
410 with sim
.write_vcd("alu_simulator.vcd"):
413 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
415 rc
= yield dec2
.e
.do
.rc
.rc
416 cridx_ok
= yield dec2
.e
.write_cr
.ok
417 cridx
= yield dec2
.e
.write_cr
.data
419 print("check extra output", repr(code
), cridx_ok
, cridx
)
421 self
.assertEqual(cridx
, 0, code
)
423 oe
= yield dec2
.e
.do
.oe
.oe
424 oe_ok
= yield dec2
.e
.do
.oe
.ok
425 if not oe
or not oe_ok
:
426 # if OE not enabled, XER SO and OV must correspondingly be false
427 so_ok
= yield alu
.n
.data_o
.xer_so
.ok
428 ov_ok
= yield alu
.n
.data_o
.xer_ov
.ok
429 self
.assertEqual(so_ok
, False, code
)
430 self
.assertEqual(ov_ok
, False, code
)
435 yield from ALUHelpers
.get_cr_a(res
, alu
, dec2
)
436 yield from ALUHelpers
.get_xer_ov(res
, alu
, dec2
)
437 yield from ALUHelpers
.get_xer_ca(res
, alu
, dec2
)
438 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
439 yield from ALUHelpers
.get_xer_so(res
, alu
, dec2
)
441 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
442 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
443 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
444 yield from ALUHelpers
.get_wr_sim_xer_ca(sim_o
, sim
, dec2
)
445 yield from ALUHelpers
.get_sim_xer_so(sim_o
, sim
, dec2
)
447 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
448 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
449 ALUHelpers
.check_xer_ca(self
, res
, sim_o
, code
)
450 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
451 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
454 if __name__
== "__main__":