src/soc/fu/compunits/compunits.py

   1 ###################################################################
   2 """Function Units Construction
   3
   4 This module pulls all of the pipelines together (soc.fu.*) and, using
   5 the regspec and Computation Unit APIs, constructs Scoreboard-aware
   6 Function Units that may systematically and automatically be wired up
   7 to appropriate Register Files.
   8
   9 Two types exist:
  10
  11 * Single-cycle Function Units.  these are FUs that will only block for
  12   one cycle.  it is expected that multiple of these be instantiated,
  13   because they are simple and trivial, and not many gates.
  14
  15   - ALU, Logical: definitely several
  16   - CR: not so many needed (perhaps)
  17   - Branch: one or two of these (depending on speculation run-ahead)
  18   - Trap: yeah really only one of these
  19   - SPR: again, only one.
  20   - ShiftRot (perhaps not too many of these)
  21
  22 * Multi-cycle (and FSM) Function Units.  these are FUs that can only
  23   handle a limited number of values, and take several cycles to complete.
  24   Given that under Scoreboard Management, start and completion must be
  25   fully managed, a "Reservation Station" style approach is required:
  26   *one* multiple-stage (N stage) pipelines need a minimum of N (plural)
  27   "CompUnit" front-ends.  this includes:
  28
  29   - MUL (all versions including MAC)
  30   - DIV (including modulo)
  31
  32 In either case, there will be multiple MultiCompUnits: it's just that
  33 single-cycle ones are instantiated individually (one single-cycle pipeline
  34 per MultiCompUnit, and multi-cycle ones need to be instantiated en-masse,
  35 where *only one* actual pipeline (or FSM) has *multiple* Reservation
  36 Stations.
  37
  38 see:
  39
  40 * https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
  41
  42 """
  43
  44 # imports
  45
  46 from nmigen import Elaboratable, Module
  47 from nmigen.cli import rtlil
  48 from soc.experiment.compalu_multi import MultiCompUnit
  49 from openpower.decoder.power_enums import Function
  50 from soc.config.test.test_loadstore import TestMemPspec
  51 from nmutil.concurrentunit import ReservationStations2
  52
  53 # pipeline / spec imports
  54
  55 from soc.fu.alu.pipeline import ALUBasePipe
  56 from soc.fu.alu.pipe_data import ALUPipeSpec
  57
  58 from soc.fu.logical.pipeline import LogicalBasePipe
  59 from soc.fu.logical.pipe_data import LogicalPipeSpec
  60
  61 from soc.fu.cr.pipeline import CRBasePipe
  62 from soc.fu.cr.pipe_data import CRPipeSpec
  63
  64 from soc.fu.branch.pipeline import BranchBasePipe
  65 from soc.fu.branch.pipe_data import BranchPipeSpec
  66
  67 from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
  68 from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
  69
  70 from soc.fu.spr.pipeline import SPRBasePipe
  71 from soc.fu.spr.pipe_data import SPRPipeSpec
  72
  73 from soc.fu.trap.pipeline import TrapBasePipe
  74 from soc.fu.trap.pipe_data import TrapPipeSpec
  75
  76 from soc.fu.div.pipeline import DivBasePipe
  77 from soc.fu.div.pipe_data import DivPipeSpecFSMDivCore
  78 from soc.fu.div.pipe_data import DivPipeSpecDivPipeCore
  79
  80 from soc.fu.mmu.fsm import FSMMMUStage
  81 from soc.fu.mmu.pipe_data import MMUPipeSpec
  82
  83 from soc.fu.mul.pipeline import MulBasePipe
  84 from soc.fu.mul.pipe_data import MulPipeSpec
  85
  86 from soc.fu.ldst.pipe_data import LDSTPipeSpec
  87 from soc.experiment.compldst_multi import LDSTCompUnit  # special-case
  88
  89
  90 ###################################################################
  91 ###### FunctionUnitBaseSingle - use to make single-stge pipes #####
  92
  93 class FunctionUnitBaseSingle(MultiCompUnit):
  94     """FunctionUnitBaseSingle
  95
  96     main "glue" class that brings everything together.
  97     ONLY use this class for single-stage pipelines.
  98
  99     * :speckls:  - the specification.  contains regspec and op subset info,
 100                    and contains common "stuff" like the pipeline ctx,
 101                    what type of nmutil pipeline base is to be used (etc)
 102     * :pipekls:  - the type of pipeline.  actually connects things together
 103
 104     note that it is through MultiCompUnit.get_in/out that we *actually*
 105     connect up the association between regspec variable names (defined
 106     in the pipe_data).
 107
 108     note that the rdflags function obtains (dynamically, from instruction
 109     decoding) which read-register ports are to be requested.  this is not
 110     ideal (it could be a lot neater) but works for now.
 111
 112     also note: additional members, fu.rd_latches and fu.wr_latches
 113     are replaced, here, by core.py.  those contain the latched
 114     read/write register information which the FU needs in order
 115     to actually read (and write) the correct register number
 116     """
 117
 118     def __init__(self, speckls, pipekls, idx):
 119         alu_name = "alu_%s%d" % (self.fnunit.name.lower(), idx)
 120         pspec = speckls(id_wid=2)                # spec (NNNPipeSpec instance)
 121         opsubset = pspec.opsubsetkls             # get the operand subset class
 122         regspec = pspec.regspec                  # get the regspec
 123         alu = pipekls(pspec)                     # create actual NNNBasePipe
 124         self.pspec = pspec
 125         super().__init__(regspec, alu, opsubset, name=alu_name)  # MultiCompUnit
 126         # these are set to None for now: core get_byregfiles fills them in
 127         # (for now)
 128         self.fu_rdlatches = None
 129         self.fu_wrlatches = None
 130
 131
 132 ##############################################################
 133 # TODO: ReservationStations-based (FunctionUnitBaseConcurrent)
 134
 135 class FunctionUnitBaseMulti(ReservationStations2):
 136     """FunctionUnitBaseMulti
 137
 138     similar to FunctionUnitBaseSingle except it creates a list
 139     of MultiCompUnit instances all using the same ALU instance.
 140
 141     * :speckls:  - the specification.  contains regspec and op subset info,
 142                    and contains common "stuff" like the pipeline ctx,
 143                    what type of nmutil pipeline base is to be used (etc)
 144     * :pipekls:  - the type of pipeline.  actually connects things together
 145
 146     * :num_rows: - number of ReservationStations wrapped around the FU
 147
 148     note that it is through MultiCompUnit.get_in/out that we *actually*
 149     connect up the association between regspec variable names (defined
 150     in the pipe_data).
 151
 152     note that the rdflags function obtains (dynamically, from instruction
 153     decoding) which read-register ports are to be requested.  this is not
 154     ideal (it could be a lot neater) but works for now.
 155     """
 156
 157     def __init__(self, speckls, pipekls, num_rows):
 158         id_wid = num_rows.bit_length()
 159         pspec = speckls(id_wid=id_wid)           # spec (NNNPipeSpec instance)
 160         opsubset = pspec.opsubsetkls             # get the operand subset class
 161         regspec = pspec.regspec                  # get the regspec
 162         alu = pipekls(pspec)                # create actual NNNBasePipe
 163         self.pspec = pspec
 164         alu_name = self.fnunit.name.lower()
 165         super().__init__(alu, num_rows, alu_name)   # initialise fan-in/fan-out
 166         self.cu = []
 167         for idx in range(num_rows):
 168             alu_name = "alu_%s%d" % (alu_name, idx)
 169             palu = self.pseudoalus[idx]
 170             cu = MultiCompUnit(regspec, palu, opsubset, name=alu_name)
 171             cu.fnunit = self.fnunit
 172             self.cu.append(cu)
 173
 174
 175 ######################################################################
 176 ###### actual Function Units: these are "single" stage pipelines #####
 177
 178 #class ALUFunctionUnit(FunctionUnitBaseSingle):
 179 class ALUFunctionUnit(FunctionUnitBaseMulti):
 180     fnunit = Function.ALU
 181
 182     def __init__(self, idx):
 183         super().__init__(ALUPipeSpec, ALUBasePipe, 1)
 184
 185
 186 #class LogicalFunctionUnit(FunctionUnitBaseSingle):
 187 class LogicalFunctionUnit(FunctionUnitBaseMulti):
 188     fnunit = Function.LOGICAL
 189
 190     def __init__(self, idx):
 191         super().__init__(LogicalPipeSpec, LogicalBasePipe, idx)
 192
 193
 194 #class CRFunctionUnit(FunctionUnitBaseSingle):
 195 class CRFunctionUnit(FunctionUnitBaseMulti):
 196     fnunit = Function.CR
 197
 198     def __init__(self, idx):
 199         super().__init__(CRPipeSpec, CRBasePipe, idx)
 200
 201
 202 #class BranchFunctionUnit(FunctionUnitBaseSingle):
 203 class BranchFunctionUnit(FunctionUnitBaseMulti):
 204     fnunit = Function.BRANCH
 205
 206     def __init__(self, idx):
 207         super().__init__(BranchPipeSpec, BranchBasePipe, idx)
 208
 209
 210 #class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
 211 class ShiftRotFunctionUnit(FunctionUnitBaseMulti):
 212     fnunit = Function.SHIFT_ROT
 213
 214     def __init__(self, idx):
 215         super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe, idx)
 216
 217
 218 class DivFSMFunctionUnit(FunctionUnitBaseSingle):
 219     fnunit = Function.DIV
 220
 221     def __init__(self, idx):
 222         super().__init__(DivPipeSpecFSMDivCore, DivBasePipe, idx)
 223
 224
 225 class MMUFSMFunctionUnit(FunctionUnitBaseSingle):
 226     fnunit = Function.MMU
 227
 228     def __init__(self, idx):
 229         super().__init__(MMUPipeSpec, FSMMMUStage, idx)
 230
 231
 232 class DivPipeFunctionUnit(FunctionUnitBaseSingle):
 233     fnunit = Function.DIV
 234
 235     def __init__(self, idx):
 236         super().__init__(DivPipeSpecDivPipeCore, DivBasePipe, idx)
 237
 238
 239 #class MulFunctionUnit(FunctionUnitBaseSingle):
 240 class MulFunctionUnit(FunctionUnitBaseMulti):
 241     fnunit = Function.MUL
 242
 243     def __init__(self, idx):
 244         super().__init__(MulPipeSpec, MulBasePipe, idx)
 245
 246
 247 class TrapFunctionUnit(FunctionUnitBaseSingle):
 248     fnunit = Function.TRAP
 249
 250     def __init__(self, idx):
 251         super().__init__(TrapPipeSpec, TrapBasePipe, idx)
 252
 253
 254 class SPRFunctionUnit(FunctionUnitBaseSingle):
 255     fnunit = Function.SPR
 256
 257     def __init__(self, idx):
 258         super().__init__(SPRPipeSpec, SPRBasePipe, idx)
 259
 260
 261 # special-case: LD/ST conforms to the CompUnit API but is not a pipeline
 262
 263 class LDSTFunctionUnit(LDSTCompUnit):
 264     fnunit = Function.LDST
 265
 266     def __init__(self, pi, awid, idx):
 267         alu_name = "ldst_%s%d" % (self.fnunit.name.lower(), idx)
 268         pspec = LDSTPipeSpec(id_wid=2)           # spec (NNNPipeSpec instance)
 269         opsubset = pspec.opsubsetkls             # get the operand subset class
 270         regspec = pspec.regspec                  # get the regspec
 271         self.opsubsetkls = opsubset
 272         super().__init__(pi, regspec, awid, opsubset, name=alu_name)
 273
 274
 275 #####################################################################
 276 ###### actual Function Units: these are "multi" stage pipelines #####
 277
 278 # TODO: ReservationStations-based.
 279
 280 # simple one-only function unit class, for test purposes
 281 class AllFunctionUnits(Elaboratable):
 282     """AllFunctionUnits
 283
 284     creates a dictionary of Function Units according to required spec.
 285     tuple is of:
 286
 287      * name of ALU,
 288      * quantity of FUs required
 289      * type of FU required
 290
 291     """
 292
 293     def __init__(self, pspec, pilist=None, div_fsm=True):
 294         addrwid = pspec.addr_wid
 295         units = pspec.units
 296         microwatt_mmu = hasattr(pspec, "mmu") and pspec.mmu == True
 297         print("AllFunctionUnits.microwatt_mmu="+str(microwatt_mmu))
 298         if not isinstance(units, dict):
 299             units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1,
 300                      'spr': 1,
 301                      'logical': 1,
 302                      'mul': 1,
 303                      'div': 1, 'shiftrot': 1}
 304             if microwatt_mmu:
 305                 units['mmu'] = 1
 306         alus = {'alu': ALUFunctionUnit,
 307                 'cr': CRFunctionUnit,
 308                 'branch': BranchFunctionUnit,
 309                 'trap': TrapFunctionUnit,
 310                 'spr': SPRFunctionUnit,
 311                 'mul': MulFunctionUnit,
 312                 'mmu': MMUFSMFunctionUnit,
 313                 'logical': LogicalFunctionUnit,
 314                 'shiftrot': ShiftRotFunctionUnit,
 315                 }
 316         if div_fsm:
 317             alus['div'] = DivFSMFunctionUnit
 318         else:
 319             alus['div'] = DivPipeFunctionUnit
 320
 321         # create dictionary of Function Units
 322         self.fus = {}
 323         self.actual_alus = {}
 324         for name, qty in units.items():
 325             kls = alus[name]
 326             if issubclass(kls, FunctionUnitBaseMulti):
 327                 fu = kls(qty) # create just the one ALU but many "fronts"
 328                 self.actual_alus[name] = fu # to be made a module of AllFUs
 329                 for i in range(qty):
 330                     self.fus["%s%d" % (name, i)] = fu.cu[i]
 331             else:
 332                 for i in range(qty):
 333                     self.fus["%s%d" % (name, i)] = kls(i)
 334
 335         # debug print for MMU ALU
 336         if microwatt_mmu:
 337             alu = self.fus["mmu0"].alu
 338             print("MMU alu", alu)
 339
 340         # if any PortInterfaces, we want LDST Units.
 341         if pilist is None:
 342             return
 343         print ("pilist", pilist)
 344         for i, pi in enumerate(pilist):
 345             self.fus["ldst%d" % (i)] = LDSTFunctionUnit(pi, addrwid, i)
 346
 347         # extract exceptions from any FunctionUnits for easy access
 348         self.excs = {}
 349         for name, alu in self.fus.items():
 350             if hasattr(alu, "exc_o"):
 351                 print ("FU exceptions", name, type(alu.exc_o), alu.exc_o)
 352                 self.excs[name] = alu.exc_o
 353
 354     def get_exc(self, name):
 355         return self.excs.get(name)
 356
 357     def get_fu(self, name):
 358         return self.fus.get(name)
 359
 360     def elaborate(self, platform):
 361         m = Module()
 362         # add MultiCompUnit modules (Single CompUnits add their own ALU)
 363         for (name, fu) in self.fus.items():
 364             setattr(m.submodules, name, fu)
 365         # if any ReservationStations, there is only one ALU per RS so add that
 366         for (name, alu) in self.actual_alus.items():
 367             setattr(m.submodules, name, alu)
 368         return m
 369
 370     def __iter__(self):
 371         for (name, fu) in self.fus.items():
 372             yield from fu.ports()
 373
 374     def ports(self):
 375         return list(self)
 376
 377
 378 def tst_single_fus_il():
 379     for (name, kls) in (('alu', ALUFunctionUnit),
 380                         ('cr', CRFunctionUnit),
 381                         ('branch', BranchFunctionUnit),
 382                         ('trap', TrapFunctionUnit),
 383                         ('spr', SPRFunctionUnit),
 384                         ('mul', MulFunctionUnit),
 385                         ('logical', LogicalFunctionUnit),
 386                         ('shiftrot', ShiftRotFunctionUnit)):
 387         fu = kls(0)
 388         vl = rtlil.convert(fu, ports=fu.ports())
 389         with open("fu_%s.il" % name, "w") as f:
 390             f.write(vl)
 391
 392
 393 def tst_all_fus():
 394     pspec = TestMemPspec(ldst_ifacetype='testpi',
 395                          imem_ifacetype='',
 396                          addr_wid=48,
 397                          mask_wid=8,
 398                          reg_wid=64)
 399     dut = AllFunctionUnits(pspec)
 400     vl = rtlil.convert(dut, ports=dut.ports())
 401     with open("all_fus.il", "w") as f:
 402         f.write(vl)
 403
 404
 405 if __name__ == '__main__':
 406     tst_single_fus_il()
 407     tst_all_fus()