1 from nmigen
import Module
, Signal
, ResetSignal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.decoder
.power_enums
import Function
9 from soc
.decoder
.isa
.all
import ISA
11 from soc
.experiment
.compalu_multi
import find_ok
# hack
14 def set_cu_input(cu
, idx
, data
):
15 rdop
= cu
.get_in_name(idx
)
16 yield cu
.src_i
[idx
].eq(data
)
18 rd_rel_o
= yield cu
.rd
.rel
[idx
]
19 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
23 yield cu
.rd
.go
[idx
].eq(1)
26 rd_rel_o
= yield cu
.rd
.rel
[idx
]
29 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
31 yield cu
.rd
.go
[idx
].eq(0)
32 yield cu
.src_i
[idx
].eq(0)
35 def get_cu_output(cu
, idx
, code
):
36 wrmask
= yield cu
.wrmask
37 wrop
= cu
.get_out_name(idx
)
38 wrok
= cu
.get_out(idx
)
39 fname
= find_ok(wrok
.fields
)
40 wrok
= yield getattr(wrok
, fname
)
41 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
42 assert wrmask
& (1<<idx
), \
43 "get_cu_output '%s': mask bit %d not set\n" \
44 "write-operand '%s' Data.ok likely not set (%s)" \
45 % (code
, idx
, wrop
, hex(wrok
))
47 wr_relall_o
= yield cu
.wr
.rel
48 wr_rel_o
= yield cu
.wr
.rel
[idx
]
49 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
53 yield cu
.wr
.go
[idx
].eq(1)
55 result
= yield cu
.dest
[idx
]
57 yield cu
.wr
.go
[idx
].eq(0)
58 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
63 def set_cu_inputs(cu
, inp
):
64 for idx
, data
in inp
.items():
65 yield from set_cu_input(cu
, idx
, data
)
68 def set_operand(cu
, dec2
, sim
):
69 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
70 yield cu
.issue_i
.eq(1)
72 yield cu
.issue_i
.eq(0)
76 def get_cu_outputs(cu
, code
):
78 wrmask
= yield cu
.wrmask
79 print ("get_cu_outputs", cu
.n_dst
, wrmask
)
80 if not wrmask
: # no point waiting (however really should doublecheck wr.rel)
82 # wait for at least one result
84 wr_rel_o
= yield cu
.wr
.rel
88 for i
in range(cu
.n_dst
):
89 wr_rel_o
= yield cu
.wr
.rel
[i
]
91 result
= yield from get_cu_output(cu
, i
, code
)
92 wrop
= cu
.get_out_name(i
)
93 print ("output", i
, wrop
, hex(result
))
98 def get_inp_indexed(cu
, inp
):
100 for i
in range(cu
.n_src
):
101 wrop
= cu
.get_in_name(i
)
107 class TestRunner(FHDLTestCase
):
108 def __init__(self
, test_data
, fukls
, iodef
, funit
):
109 super().__init
__("run_all")
110 self
.test_data
= test_data
118 instruction
= Signal(32)
120 pdecode
= create_pdecode()
122 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
123 if self
.funit
== Function
.LDST
:
124 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
125 m
.submodules
.l0
= l0
= TstL0CacheBuffer(n_units
=1, regwid
=64,
127 pi
= l0
.l0
.dports
[0].pi
128 m
.submodules
.cu
= cu
= self
.fukls(pi
, awid
=3)
129 m
.d
.comb
+= cu
.ad
.go
.eq(cu
.ad
.rel
) # link addr-go direct to rel
130 m
.d
.comb
+= cu
.st
.go
.eq(cu
.st
.rel
) # link store-go direct to rel
132 m
.submodules
.cu
= cu
= self
.fukls()
134 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
140 yield cu
.issue_i
.eq(0)
143 for test
in self
.test_data
:
145 program
= test
.program
146 self
.subTest(test
.name
)
147 print ("test", test
.name
, test
.mem
)
148 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
150 gen
= program
.generate_instructions()
151 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
154 if self
.funit
== Function
.LDST
:
156 print ("before, init mem", mem
.depth
, mem
.width
, mem
)
157 for i
in range(mem
.depth
//2):
158 data
= sim
.mem
.ld(i
*16, 8)
159 data1
= sim
.mem
.ld(i
*16+8, 8)
160 print ("init ", i
, hex(data
), hex(data1
))
161 yield mem
._array
[i
].eq(data |
(data1
<<32))
163 for k
, v
in sim
.mem
.mem
.items():
164 print (" %6x %016x" % (k
, v
))
165 print ("before, nmigen mem dump")
166 for i
in range(mem
.depth
//2):
167 actual_mem
= yield mem
._array
[i
]
168 print (" %6i %016x" % (i
*2, actual_mem
))
171 index
= sim
.pc
.CIA
.value
//4
172 while index
< len(instructions
):
173 ins
, code
= instructions
[index
]
175 print("0x{:X}".format(ins
& 0xffffffff))
178 # ask the decoder to decode this binary data (endian'd)
179 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
180 yield instruction
.eq(ins
) # raw binary instr.
182 fn_unit
= yield pdecode2
.e
.fn_unit
183 fuval
= self
.funit
.value
184 self
.assertEqual(fn_unit
& fuval
, fuval
)
186 # set operand and get inputs
187 yield from set_operand(cu
, pdecode2
, sim
)
188 iname
= yield from self
.iodef
.get_cu_inputs(pdecode2
, sim
)
189 inp
= get_inp_indexed(cu
, iname
)
191 # reset read-operand mask
192 rdmask
= pdecode2
.rdflags(cu
)
193 #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
194 #print ("decoder rdmask", rdmask)
195 yield cu
.rdmaskn
.eq(~rdmask
)
197 # reset write-operand mask
198 for idx
in range(cu
.n_dst
):
199 wrok
= cu
.get_out(idx
)
200 fname
= find_ok(wrok
.fields
)
201 yield getattr(wrok
, fname
).eq(0)
206 rd_rel_o
= yield cu
.rd
.rel
207 wr_rel_o
= yield cu
.wr
.rel
208 print ("before inputs, rd_rel, wr_rel: ",
209 bin(rd_rel_o
), bin(wr_rel_o
))
210 assert wr_rel_o
== 0, "wr.rel %s must be zero. "\
211 "previous instr not written all regs\n"\
213 (bin(wr_rel_o
), cu
.rwid
[1])
214 yield from set_cu_inputs(cu
, inp
)
215 rd_rel_o
= yield cu
.rd
.rel
216 wr_rel_o
= yield cu
.wr
.rel
217 wrmask
= yield cu
.wrmask
218 print ("after inputs, rd_rel, wr_rel, wrmask: ",
219 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
221 # call simulated operation
222 opname
= code
.split(' ')[0]
223 yield from sim
.call(opname
)
224 index
= sim
.pc
.CIA
.value
//4
227 # get all outputs (one by one, just "because")
228 res
= yield from get_cu_outputs(cu
, code
)
229 wrmask
= yield cu
.wrmask
230 rd_rel_o
= yield cu
.rd
.rel
231 wr_rel_o
= yield cu
.wr
.rel
232 print ("after got outputs, rd_rel, wr_rel, wrmask: ",
233 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
235 # wait for busy to go low
237 busy_o
= yield cu
.busy_o
238 print ("busy", busy_o
)
243 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
246 # sigh. hard-coded. test memory
247 if self
.funit
== Function
.LDST
:
249 print ("sim mem dump")
250 for k
, v
in sim
.mem
.mem
.items():
251 print (" %6x %016x" % (k
, v
))
252 print ("nmigen mem dump")
253 for i
in range(mem
.depth
//2):
254 actual_mem
= yield mem
._array
[i
]
255 print (" %6i %016x" % (i
*2, actual_mem
))
257 for i
in range(mem
.depth
//2):
258 data
= sim
.mem
.ld(i
*16, 8)
259 data1
= sim
.mem
.ld(i
*16+8, 8)
260 expected_mem
= (data |
(data1
<<32))
261 actual_mem
= yield mem
._array
[i
]
262 self
.assertEqual(expected_mem
, actual_mem
,
263 "%s %d %x %x" % (code
, i
,
264 expected_mem
, actual_mem
))
267 sim
.add_sync_process(process
)
269 name
= self
.funit
.name
.lower()
270 with sim
.write_vcd("%s_simulator.vcd" % name
,
271 "%s_simulator.gtkw" % name
,