branch output spec nia not cia
[soc.git] / src / soc / fu / cr / pipe_data.py
1 from nmigen import Signal, Const
2 from ieee754.fpcommon.getop import FPPipeContext
3 from soc.fu.alu.pipe_data import IntegerData
4 from nmutil.dynamicpipe import SimpleHandshakeRedir
5 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
6
7
8 class CRInputData(IntegerData):
9 regspec = [('INT', 'a', '0:63'),
10 ('CR', 'cr', '32')]
11 def __init__(self, pspec):
12 super().__init__(pspec)
13 self.a = Signal(64, reset_less=True) # RA
14 self.cr = Signal(32, reset_less=True) # CR in
15
16 def __iter__(self):
17 yield from super().__iter__()
18 yield self.a
19 yield self.cr
20
21 def eq(self, i):
22 lst = super().eq(i)
23 return lst + [self.a.eq(i.a),
24 self.cr.eq(i.cr)]
25
26 class CROutputData(IntegerData):
27 regspec = [('INT', 'o', '0:63'),
28 ('CR', 'cr', '32')]
29 def __init__(self, pspec):
30 super().__init__(pspec)
31 self.o = Signal(64, reset_less=True) # RA
32 self.cr = Signal(32, reset_less=True, name="cr_out") # CR in
33
34 def __iter__(self):
35 yield from super().__iter__()
36 yield self.o
37 yield self.cr
38
39 def eq(self, i):
40 lst = super().eq(i)
41 return lst + [self.o.eq(i.o),
42 self.cr.eq(i.cr)]
43
44 # TODO: replace CompALUOpSubset with CompCROpSubset
45 class CRPipeSpec:
46 regspec = (CRInputData.regspec, CROutputData.regspec)
47 opsubsetkls = CompALUOpSubset
48 def __init__(self, id_wid, op_wid):
49 self.id_wid = id_wid
50 self.op_wid = op_wid
51 self.opkls = lambda _: self.opsubsetkls(name="op")
52 self.stage = None
53 self.pipekls = SimpleHandshakeRedir