1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
, ALUHelpers
16 from soc
.fu
.cr
.pipeline
import CRBasePipe
17 from soc
.fu
.cr
.pipe_data
import CRPipeSpec
22 # This test bench is a bit different than is usual. Initially when I
23 # was writing it, I had all of the tests call a function to create a
24 # device under test and simulator, initialize the dut, run the
25 # simulation for ~2 cycles, and assert that the dut output what it
26 # should have. However, this was really slow, since it needed to
27 # create and tear down the dut and simulator for every test case.
29 # Now, instead of doing that, every test case in ALUTestCase puts some
30 # data into the test_data list below, describing the instructions to
31 # be tested and the initial state. Once all the tests have been run,
32 # test_data gets passed to TestRunner which then sets up the DUT and
33 # simulator once, runs all the data through it, and asserts that the
34 # results match the pseudocode sim at every cycle.
36 # By doing this, I've reduced the time it takes to run the test suite
37 # massively. Before, it took around 1 minute on my computer, now it
38 # takes around 3 seconds
41 class CRTestCase(FHDLTestCase
):
43 def __init__(self
, name
):
44 super().__init
__(name
)
47 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
49 tc
= TestCase(prog
, self
.test_name
,
50 regs
=initial_regs
, sprs
=initial_sprs
, cr
=initial_cr
)
51 self
.test_data
.append(tc
)
54 insns
= ["crand", "cror", "crnand", "crnor", "crxor", "creqv",
57 choice
= random
.choice(insns
)
58 ba
= random
.randint(0, 31)
59 bb
= random
.randint(0, 31)
60 bt
= random
.randint(0, 31)
61 lst
= [f
"{choice} {ba}, {bb}, {bt}"]
62 cr
= random
.randint(0, (1<<32)-1)
63 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
67 lst
= ["crand 0, 11, 13"]
68 cr
= random
.randint(0, (1<<32)-1)
69 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
71 def test_1_mcrf(self
):
73 src
= random
.randint(0, 7)
74 dst
= random
.randint(0, 7)
75 lst
= [f
"mcrf {src}, {dst}"]
76 cr
= random
.randint(0, (1<<32)-1)
77 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
79 def test_0_mcrf(self
):
81 lst
= [f
"mcrf 5, {i}"]
83 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
87 mask
= random
.randint(0, 255)
88 lst
= [f
"mtcrf {mask}, 2"]
89 cr
= random
.randint(0, (1<<32)-1)
90 initial_regs
= [0] * 32
91 initial_regs
[2] = random
.randint(0, (1<<32)-1)
92 self
.run_tst_program(Program(lst
), initial_regs
=initial_regs
,
94 def test_mtocrf(self
):
96 mask
= 1<<random
.randint(0, 7)
97 lst
= [f
"mtocrf {mask}, 2"]
98 cr
= random
.randint(0, (1<<32)-1)
99 initial_regs
= [0] * 32
100 initial_regs
[2] = random
.randint(0, (1<<32)-1)
101 self
.run_tst_program(Program(lst
), initial_regs
=initial_regs
,
107 cr
= random
.randint(0, (1<<32)-1)
108 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
110 def test_mfocrf(self
):
112 mask
= 1<<random
.randint(0, 7)
113 lst
= [f
"mfocrf 2, {mask}"]
114 cr
= random
.randint(0, (1<<32)-1)
115 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
119 bc
= random
.randint(0, 31)
120 lst
= [f
"isel 1, 2, 3, {bc}"]
121 cr
= random
.randint(0, (1<<32)-1)
122 initial_regs
= [0] * 32
123 initial_regs
[2] = random
.randint(0, (1<<64)-1)
124 initial_regs
[3] = random
.randint(0, (1<<64)-1)
125 #initial_regs[2] = i*2
126 #initial_regs[3] = i*2+1
127 self
.run_tst_program(Program(lst
),
128 initial_regs
=initial_regs
, initial_cr
=cr
)
132 bfa
= random
.randint(0, 7)
133 lst
= [f
"setb 1, {bfa}"]
134 cr
= random
.randint(0, (1<<32)-1)
135 self
.run_tst_program(Program(lst
), initial_cr
=cr
)
139 def test_ilang(self
):
140 pspec
= CRPipeSpec(id_wid
=2)
141 alu
= CRBasePipe(pspec
)
142 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
143 with
open("cr_pipeline.il", "w") as f
:
147 def get_cu_inputs(dec2
, sim
):
148 """naming (res) must conform to CRFunctionUnit input regspec
151 full_reg
= yield dec2
.e
.do
.read_cr_whole
154 print(sim
.cr
.get_range().value
)
156 res
['full_cr'] = sim
.cr
.get_range().value
159 cr1_en
= yield dec2
.e
.read_cr1
.ok
161 cr1_sel
= yield dec2
.e
.read_cr1
.data
162 res
['cr_a'] = sim
.crl
[cr1_sel
].get_range().value
163 cr2_en
= yield dec2
.e
.read_cr2
.ok
166 cr2_sel
= yield dec2
.e
.read_cr2
.data
167 res
['cr_b'] = sim
.crl
[cr2_sel
].get_range().value
168 cr3_en
= yield dec2
.e
.read_cr3
.ok
171 cr3_sel
= yield dec2
.e
.read_cr3
.data
172 res
['cr_c'] = sim
.crl
[cr3_sel
].get_range().value
175 reg1_ok
= yield dec2
.e
.read_reg1
.ok
177 data1
= yield dec2
.e
.read_reg1
.data
178 res
['ra'] = sim
.gpr(data1
).value
181 reg2_ok
= yield dec2
.e
.read_reg2
.ok
183 data2
= yield dec2
.e
.read_reg2
.data
184 res
['rb'] = sim
.gpr(data2
).value
186 print ("get inputs", res
)
190 class TestRunner(FHDLTestCase
):
191 def __init__(self
, test_data
):
192 super().__init
__("run_all")
193 self
.test_data
= test_data
195 def set_inputs(self
, alu
, dec2
, simulator
):
196 inp
= yield from get_cu_inputs(dec2
, simulator
)
197 yield from ALUHelpers
.set_full_cr(alu
, dec2
, inp
)
198 yield from ALUHelpers
.set_cr_a(alu
, dec2
, inp
)
199 yield from ALUHelpers
.set_cr_b(alu
, dec2
, inp
)
200 yield from ALUHelpers
.set_cr_c(alu
, dec2
, inp
)
201 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
202 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
204 def assert_outputs(self
, alu
, dec2
, simulator
, code
):
205 whole_reg
= yield dec2
.e
.do
.write_cr_whole
206 cr_en
= yield dec2
.e
.write_cr
.ok
208 full_cr
= yield alu
.n
.data_o
.full_cr
.data
209 expected_cr
= simulator
.cr
.get_range().value
210 print(f
"CR whole: expected {expected_cr:x}, actual: {full_cr:x}")
211 self
.assertEqual(expected_cr
, full_cr
, code
)
213 cr_sel
= yield dec2
.e
.write_cr
.data
214 expected_cr
= simulator
.cr
.get_range().value
215 print(f
"CR whole: {expected_cr:x}, sel {cr_sel}")
216 expected_cr
= simulator
.crl
[cr_sel
].get_range().value
217 real_cr
= yield alu
.n
.data_o
.cr
.data
218 print(f
"CR part: expected {expected_cr:x}, actual: {real_cr:x}")
219 self
.assertEqual(expected_cr
, real_cr
, code
)
220 alu_out
= yield alu
.n
.data_o
.o
.data
221 out_reg_valid
= yield dec2
.e
.write_reg
.ok
223 write_reg_idx
= yield dec2
.e
.write_reg
.data
224 expected
= simulator
.gpr(write_reg_idx
).value
225 print(f
"expected {expected:x}, actual: {alu_out:x}")
226 self
.assertEqual(expected
, alu_out
, code
)
231 instruction
= Signal(32)
233 pdecode
= create_pdecode()
235 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
237 pspec
= CRPipeSpec(id_wid
=2)
238 m
.submodules
.alu
= alu
= CRBasePipe(pspec
)
240 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
241 comb
+= alu
.n
.ready_i
.eq(1)
242 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
247 for test
in self
.test_data
:
249 program
= test
.program
250 self
.subTest(test
.name
)
251 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
253 gen
= program
.generate_instructions()
254 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
256 index
= sim
.pc
.CIA
.value
//4
257 while index
< len(instructions
):
258 ins
, code
= instructions
[index
]
260 print("0x{:X}".format(ins
& 0xffffffff))
263 # ask the decoder to decode this binary data (endian'd)
264 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
265 yield instruction
.eq(ins
) # raw binary instr.
267 yield from self
.set_inputs(alu
, pdecode2
, sim
)
268 yield alu
.p
.valid_i
.eq(1)
269 fn_unit
= yield pdecode2
.e
.do
.fn_unit
270 self
.assertEqual(fn_unit
, Function
.CR
.value
, code
)
272 opname
= code
.split(' ')[0]
273 yield from sim
.call(opname
)
274 index
= sim
.pc
.CIA
.value
//4
276 vld
= yield alu
.n
.valid_o
279 vld
= yield alu
.n
.valid_o
281 yield from self
.assert_outputs(alu
, pdecode2
, sim
, code
)
283 sim
.add_sync_process(process
)
284 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
289 if __name__
== "__main__":
290 unittest
.main(exit
=False)
291 suite
= unittest
.TestSuite()
292 suite
.addTest(TestRunner(CRTestCase
.test_data
))
294 runner
= unittest
.TextTestRunner()