1 from nmutil
.singlepipe
import ControlBase
2 from nmutil
.pipemodbase
import PipeModBaseChain
3 from soc
.fu
.mul
.output_stage
import DivMulOutputStage
4 from soc
.fu
.div
.input_stage
import DivMulInputStage
5 from soc
.fu
.div
.output_stage
import DivOutputStage
6 from soc
.fu
.div
.setup_stage
import DivSetupStage
7 from soc
.fu
.div
.core_stages
import (DivCoreSetupStage
, DivCoreCalculateStage
,
11 class DivStagesStart(PipeModBaseChain
):
13 alu_input
= DivMulInputStage(self
.pspec
)
14 div_setup
= DivSetupStage(self
.pspec
)
15 core_setup
= DivCoreSetupStage(self
.pspec
)
16 return [alu_input
, div_setup
, core_setup
]
19 class DivStagesMiddle(PipeModBaseChain
):
20 def __init__(self
, pspec
, stage_start_index
, stage_end_index
):
21 self
.stage_start_index
= stage_start_index
22 self
.stage_end_index
= stage_end_index
23 super().__init
__(pspec
)
27 for index
in range(self
.stage_start_index
, self
.stage_end_index
):
28 stages
.append(DivCoreCalculateStage(self
.pspec
, index
))
32 class DivStagesEnd(PipeModBaseChain
):
34 core_final
= DivCoreFinalStage(self
.pspec
)
35 div_out
= DivOutputStage(self
.pspec
)
36 alu_out
= DivMulOutputStage(self
.pspec
)
37 self
.div_out
= div_out
# debugging - bug #425
38 return [core_final
, div_out
, alu_out
]
41 class DIVBasePipe(ControlBase
):
42 def __init__(self
, pspec
, compute_steps_per_stage
=4):
43 ControlBase
.__init
__(self
)
44 self
.pipe_start
= DivStagesStart(pspec
)
45 compute_steps
= pspec
.core_config
.n_stages
46 self
.pipe_middles
= []
47 for start
in range(0, compute_steps
, compute_steps_per_stage
):
48 end
= min(start
+ compute_steps_per_stage
, compute_steps
)
49 self
.pipe_middles
.append(DivStagesMiddle(pspec
, start
, end
))
50 self
.pipe_end
= DivStagesEnd(pspec
)
51 self
._eqs
= self
.connect([self
.pipe_start
,
55 def elaborate(self
, platform
):
56 m
= ControlBase
.elaborate(self
, platform
)
57 m
.submodules
.pipe_start
= self
.pipe_start
58 for i
in self
.pipe_middles
:
59 name
= f
"pipe_{i.stage_start_index}_to_{i.stage_end_index}"
60 setattr(m
.submodules
, name
, i
)
61 m
.submodules
.pipe_end
= self
.pipe_end