1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import (TestCase
, ALUHelpers
)
16 from soc
.fu
.div
.pipeline
import DIVBasePipe
17 from soc
.fu
.div
.pipe_data
import DIVPipeSpec
21 def get_cu_inputs(dec2
, sim
):
22 """naming (res) must conform to DIVFunctionUnit input regspec
26 yield from ALUHelpers
.get_sim_int_ra(res
, sim
, dec2
) # RA
27 yield from ALUHelpers
.get_sim_int_rb(res
, sim
, dec2
) # RB
28 yield from ALUHelpers
.get_sim_xer_so(res
, sim
, dec2
) # XER.so
30 print ("alu get_cu_inputs", res
)
36 def set_alu_inputs(alu
, dec2
, sim
):
37 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
38 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
39 # and place it into data_i.b
41 inp
= yield from get_cu_inputs(dec2
, sim
)
42 yield from ALUHelpers
.set_int_ra(alu
, dec2
, inp
)
43 yield from ALUHelpers
.set_int_rb(alu
, dec2
, inp
)
45 yield from ALUHelpers
.set_xer_so(alu
, dec2
, inp
)
48 # This test bench is a bit different than is usual. Initially when I
49 # was writing it, I had all of the tests call a function to create a
50 # device under test and simulator, initialize the dut, run the
51 # simulation for ~2 cycles, and assert that the dut output what it
52 # should have. However, this was really slow, since it needed to
53 # create and tear down the dut and simulator for every test case.
55 # Now, instead of doing that, every test case in DIVTestCase puts some
56 # data into the test_data list below, describing the instructions to
57 # be tested and the initial state. Once all the tests have been run,
58 # test_data gets passed to TestRunner which then sets up the DUT and
59 # simulator once, runs all the data through it, and asserts that the
60 # results match the pseudocode sim at every cycle.
62 # By doing this, I've reduced the time it takes to run the test suite
63 # massively. Before, it took around 1 minute on my computer, now it
64 # takes around 3 seconds
67 class DIVTestCase(FHDLTestCase
):
70 def __init__(self
, name
):
71 super().__init
__(name
)
74 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None):
75 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
)
76 self
.test_data
.append(tc
)
78 def tst_0_regression(self
):
80 lst
= ["divwo 3, 1, 2"]
81 initial_regs
= [0] * 32
82 initial_regs
[1] = 0xbc716835f32ac00c
83 initial_regs
[2] = 0xcdf69a7f7042db66
84 self
.run_tst_program(Program(lst
), initial_regs
)
86 def tst_1_regression(self
):
87 lst
= ["divwo 3, 1, 2"]
88 initial_regs
= [0] * 32
89 initial_regs
[1] = 0x10000000000000000-4
90 initial_regs
[2] = 0x10000000000000000-2
91 self
.run_tst_program(Program(lst
), initial_regs
)
93 def tst_2_regression(self
):
94 lst
= ["divwo 3, 1, 2"]
95 initial_regs
= [0] * 32
96 initial_regs
[1] = 0xffffffffffff9321
97 initial_regs
[2] = 0xffffffffffff7012
98 self
.run_tst_program(Program(lst
), initial_regs
)
100 def tst_3_regression(self
):
101 lst
= ["divwo. 3, 1, 2"]
102 initial_regs
= [0] * 32
103 initial_regs
[1] = 0x1b8e32f2458746af
104 initial_regs
[2] = 0x6b8aee2ccf7d62e9
105 self
.run_tst_program(Program(lst
), initial_regs
)
107 def tst_4_regression(self
):
108 lst
= ["divw 3, 1, 2"]
109 initial_regs
= [0] * 32
110 initial_regs
[1] = 0x1c4e6c2f3aa4a05c
111 initial_regs
[2] = 0xe730c2eed6cc8dd7
112 self
.run_tst_program(Program(lst
), initial_regs
)
114 def tst_5_regression(self
):
115 lst
= ["divw 3, 1, 2",
117 initial_regs
= [0] * 32
118 initial_regs
[1] = 0x1c4e6c2f3aa4a05c
119 initial_regs
[2] = 0xe730c2eed6cc8dd7
120 initial_regs
[4] = 0x1b8e32f2458746af
121 initial_regs
[5] = 0x6b8aee2ccf7d62e9
122 self
.run_tst_program(Program(lst
), initial_regs
)
124 def test_6_regression(self
):
125 # CR0 not getting set properly for this one
126 # turns out that overflow is not set correctly in
127 # fu/div/output_stage.py calc_overflow
128 # https://bugs.libre-soc.org/show_bug.cgi?id=425
129 lst
= ["divw. 3, 1, 2"]
130 initial_regs
= [0] * 32
131 initial_regs
[1] = 0x61c1cc3b80f2a6af
132 initial_regs
[2] = 0x9dc66a7622c32bc0
133 self
.run_tst_program(Program(lst
), initial_regs
)
135 def tst_rand_divw(self
):
136 insns
= ["divw", "divw.", "divwo", "divwo."]
138 choice
= random
.choice(insns
)
139 lst
= [f
"{choice} 3, 1, 2"]
140 initial_regs
= [0] * 32
141 initial_regs
[1] = random
.randint(0, (1<<64)-1)
142 initial_regs
[2] = random
.randint(0, (1<<64)-1)
143 self
.run_tst_program(Program(lst
), initial_regs
)
146 pspec
= DIVPipeSpec(id_wid
=2)
147 alu
= DIVBasePipe(pspec
)
148 vl
= rtlil
.convert(alu
, ports
=alu
.ports())
149 with
open("div_pipeline.il", "w") as f
:
153 class TestRunner(FHDLTestCase
):
154 def __init__(self
, test_data
):
155 super().__init
__("run_all")
156 self
.test_data
= test_data
161 instruction
= Signal(32)
163 pdecode
= create_pdecode()
165 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
167 pspec
= DIVPipeSpec(id_wid
=2)
168 m
.submodules
.alu
= alu
= DIVBasePipe(pspec
)
170 comb
+= alu
.p
.data_i
.ctx
.op
.eq_from_execute1(pdecode2
.e
)
171 comb
+= alu
.n
.ready_i
.eq(1)
172 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
177 for test
in self
.test_data
:
179 program
= test
.program
180 self
.subTest(test
.name
)
181 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, test
.cr
,
183 gen
= program
.generate_instructions()
184 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
187 index
= sim
.pc
.CIA
.value
//4
188 while index
< len(instructions
):
189 ins
, code
= instructions
[index
]
191 print("instruction: 0x{:X}".format(ins
& 0xffffffff))
194 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
195 ov
= 1 if sim
.spr
['XER'][XER_bits
['OV']] else 0
196 ov32
= 1 if sim
.spr
['XER'][XER_bits
['OV32']] else 0
197 print ("before: so/ov/32", so
, ov
, ov32
)
199 # ask the decoder to decode this binary data (endian'd)
200 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
201 yield instruction
.eq(ins
) # raw binary instr.
203 fn_unit
= yield pdecode2
.e
.do
.fn_unit
204 self
.assertEqual(fn_unit
, Function
.DIV
.value
)
205 yield from set_alu_inputs(alu
, pdecode2
, sim
)
207 # set valid for one cycle, propagate through pipeline...
208 yield alu
.p
.valid_i
.eq(1)
210 yield alu
.p
.valid_i
.eq(0)
212 opname
= code
.split(' ')[0]
213 yield from sim
.call(opname
)
214 index
= sim
.pc
.CIA
.value
//4
216 vld
= yield alu
.n
.valid_o
219 vld
= yield alu
.n
.valid_o
220 # bug #425 investigation
221 do
= alu
.pipe_end
.div_out
223 is_32bit
= yield ctx_op
.is_32bit
224 is_signed
= yield ctx_op
.is_signed
225 quotient_root
= yield do
.i
.core
.quotient_root
226 dive_abs_ov32
= yield do
.i
.dive_abs_ov32
227 div_by_zero
= yield do
.i
.div_by_zero
228 quotient_neg
= yield do
.quotient_neg
229 print ("32bit", hex(is_32bit
))
230 print ("signed", hex(is_signed
))
231 print ("quotient_root", hex(quotient_root
))
232 print ("div_by_zero", hex(div_by_zero
))
233 print ("dive_abs_ov32", hex(dive_abs_ov32
))
234 print ("quotient_neg", hex(quotient_neg
))
238 yield from self
.check_alu_outputs(alu
, pdecode2
, sim
, code
)
241 sim
.add_sync_process(process
)
242 with sim
.write_vcd("div_simulator.vcd", "div_simulator.gtkw",
246 def check_alu_outputs(self
, alu
, dec2
, sim
, code
):
248 rc
= yield dec2
.e
.do
.rc
.data
249 cridx_ok
= yield dec2
.e
.write_cr
.ok
250 cridx
= yield dec2
.e
.write_cr
.data
252 print ("check extra output", repr(code
), cridx_ok
, cridx
)
254 self
.assertEqual(cridx
, 0, code
)
259 yield from ALUHelpers
.get_cr_a(res
, alu
, dec2
)
260 yield from ALUHelpers
.get_xer_ov(res
, alu
, dec2
)
261 yield from ALUHelpers
.get_int_o(res
, alu
, dec2
)
262 yield from ALUHelpers
.get_xer_so(res
, alu
, dec2
)
264 print ("res output", res
)
266 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
267 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
268 yield from ALUHelpers
.get_sim_xer_ov(sim_o
, sim
, dec2
)
269 yield from ALUHelpers
.get_sim_xer_so(sim_o
, sim
, dec2
)
271 print ("sim output", sim_o
)
273 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
274 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
275 ALUHelpers
.check_xer_ov(self
, res
, sim_o
, code
)
276 ALUHelpers
.check_xer_so(self
, res
, sim_o
, code
)
278 oe
= yield dec2
.e
.do
.oe
.oe
279 oe_ok
= yield dec2
.e
.do
.oe
.ok
280 print ("oe, oe_ok", oe
, oe_ok
)
281 if not oe
or not oe_ok
:
282 # if OE not enabled, XER SO and OV must not be activated
283 so_ok
= yield alu
.n
.data_o
.xer_so
.ok
284 ov_ok
= yield alu
.n
.data_o
.xer_ov
.ok
285 print ("so, ov", so_ok
, ov_ok
)
286 self
.assertEqual(ov_ok
, False, code
)
287 self
.assertEqual(so_ok
, False, code
)
290 if __name__
== "__main__":
291 unittest
.main(exit
=False)
292 suite
= unittest
.TestSuite()
293 suite
.addTest(TestRunner(DIVTestCase
.test_data
))
295 runner
= unittest
.TextTestRunner()