3 based on microwatt loadstore1.vhdl
7 * https://bugs.libre-soc.org/show_bug.cgi?id=465
11 from nmigen
import (Elaboratable
, Module
, Signal
, Shape
, unsigned
, Cat
, Mux
,
14 from nmutil
.util
import rising_edge
15 from enum
import Enum
, unique
17 from soc
.experiment
.dcache
import DCache
18 from soc
.experiment
.pimem
import PortInterfaceBase
19 from soc
.experiment
.mem_types
import LoadStore1ToMMUType
20 from soc
.experiment
.mem_types
import MMUToLoadStore1Type
22 from soc
.minerva
.wishbone
import make_wb_layout
23 from soc
.bus
.sram
import SRAM
28 IDLE
= 0 # ready for instruction
29 SECOND_REQ
= 1 # send 2nd request of unaligned xfer
30 ACK_WAIT
= 2 # waiting for ack from dcache
31 MMU_LOOKUP
= 3 # waiting for MMU to look up translation
32 TLBIE_WAIT
= 4 # waiting for MMU to finish doing a tlbie
33 FINISH_LFS
= 5 # write back converted SP data for lfs*
34 COMPLETE
= 6 # extra cycle to complete an operation
37 # glue logic for microwatt mmu and dcache
38 class LoadStore1(PortInterfaceBase
):
39 def __init__(self
, pspec
):
41 self
.disable_cache
= (hasattr(pspec
, "disable_cache") and
42 pspec
.disable_cache
== True)
43 regwid
= pspec
.reg_wid
44 addrwid
= pspec
.addr_wid
46 super().__init
__(regwid
, addrwid
)
47 self
.dcache
= DCache()
48 self
.d_in
= self
.dcache
.d_in
49 self
.d_out
= self
.dcache
.d_out
50 self
.l_in
= LoadStore1ToMMUType()
51 self
.l_out
= MMUToLoadStore1Type()
53 self
.mmureq
= Signal()
54 self
.derror
= Signal()
56 # TODO, convert dcache wb_in/wb_out to "standard" nmigen Wishbone bus
57 self
.dbus
= Record(make_wb_layout(pspec
))
59 # for creating a single clock blip to DCache
60 self
.d_valid
= Signal()
61 self
.d_w_valid
= Signal()
62 self
.d_validblip
= Signal()
64 # DSISR and DAR cached values. note that the MMU FSM is where
65 # these are accessed by OP_MTSPR/OP_MFSPR, on behalf of LoadStore1.
66 # by contrast microwatt has the spr set/get done *in* loadstore1.vhdl
67 self
.dsisr
= Signal(64)
70 # state info for LD/ST
72 # latch most of the input request
76 self
.addr
= Signal(64)
77 self
.store_data
= Signal(64)
78 self
.load_data
= Signal(64)
79 self
.byte_sel
= Signal(8)
80 self
.update
= Signal()
81 #self.xerc : xer_common_t;
82 #self.reserve = Signal()
83 #self.atomic = Signal()
84 #self.atomic_last = Signal()
86 self
.nc
= Signal() # non-cacheable access
87 self
.virt_mode
= Signal()
88 self
.priv_mode
= Signal()
89 self
.state
= Signal(State
)
90 self
.instr_fault
= Signal()
91 self
.align_intr
= Signal()
93 self
.wait_dcache
= Signal()
94 self
.wait_mmu
= Signal()
95 #self.mode_32bit = Signal()
96 self
.wr_sel
= Signal(2)
97 self
.interrupt
= Signal()
98 #self.intr_vec : integer range 0 to 16#fff#;
99 #self.nia = Signal(64)
100 #self.srr1 = Signal(16)
103 with m
.Switch(self
.state
):
104 with m
.Case(State
.IDLE
):
106 with m
.Case(State
.SECOND_REQ
):
108 # v.state.eq(ACK_WAIT)
109 # v.last_dword.eq(0);
111 with m
.Case(State
.ACK_WAIT
):
113 with m
.Case(State
.MMU_LOOKUP
):
115 with m
.Case(State
.TLBIE_WAIT
):
117 with m
.Case(State
.FINISH_LFS
):
119 with m
.Case(State
.COMPLETE
):
122 def set_wr_addr(self
, m
, addr
, mask
, misalign
):
123 m
.d
.comb
+= self
.load
.eq(0) # store operation
125 m
.d
.comb
+= self
.d_in
.load
.eq(0)
126 m
.d
.comb
+= self
.byte_sel
.eq(mask
)
127 m
.d
.comb
+= self
.addr
.eq(addr
)
128 m
.d
.comb
+= self
.align_intr
.eq(misalign
)
129 # option to disable the cache entirely for write
130 if self
.disable_cache
:
131 m
.d
.comb
+= self
.nc
.eq(1)
134 def set_rd_addr(self
, m
, addr
, mask
, misalign
):
135 m
.d
.comb
+= self
.d_valid
.eq(1)
136 m
.d
.comb
+= self
.d_in
.valid
.eq(self
.d_validblip
)
137 m
.d
.comb
+= self
.load
.eq(1) # load operation
138 m
.d
.comb
+= self
.d_in
.load
.eq(1)
139 m
.d
.comb
+= self
.byte_sel
.eq(mask
)
140 m
.d
.comb
+= self
.align_intr
.eq(misalign
)
141 m
.d
.comb
+= self
.addr
.eq(addr
)
142 # BAD HACK! disable cacheing on LD when address is 0xCxxx_xxxx
143 # this is for peripherals. same thing done in Microwatt loadstore1.vhdl
144 with m
.If(addr
[28:] == Const(0xc, 4)):
145 m
.d
.comb
+= self
.nc
.eq(1)
146 # option to disable the cache entirely for read
147 if self
.disable_cache
:
148 m
.d
.comb
+= self
.nc
.eq(1)
149 return None #FIXME return value
151 def set_wr_data(self
, m
, data
, wen
):
152 # do the "blip" on write data
153 m
.d
.comb
+= self
.d_valid
.eq(1)
154 m
.d
.comb
+= self
.d_in
.valid
.eq(self
.d_validblip
)
155 # put data into comb which is picked up in main elaborate()
156 m
.d
.comb
+= self
.d_w_valid
.eq(1)
157 m
.d
.comb
+= self
.store_data
.eq(data
)
158 #m.d.sync += self.d_in.byte_sel.eq(wen) # this might not be needed
159 st_ok
= self
.done
# TODO indicates write data is valid
162 def get_rd_data(self
, m
):
163 ld_ok
= self
.done
# indicates read data is valid
164 data
= self
.load_data
# actual read data
168 if d_in.error = '1' then
169 if d_in.cache_paradox = '1' then
170 -- signal an interrupt straight away
172 dsisr(63 - 38) := not r2.req.load;
173 -- XXX there is no architected bit for this
174 -- (probably should be a machine check in fact)
175 dsisr(63 - 35) := d_in.cache_paradox;
177 -- Look up the translation for TLB miss
178 -- and also for permission error and RC error
179 -- in case the PTE has been updated.
181 v.state := MMU_LOOKUP;
187 def elaborate(self
, platform
):
188 m
= super().elaborate(platform
)
189 comb
, sync
= m
.d
.comb
, m
.d
.sync
191 # create dcache module
192 m
.submodules
.dcache
= dcache
= self
.dcache
195 d_in
, d_out
, l_out
, dbus
= self
.d_in
, self
.d_out
, self
.l_out
, self
.dbus
197 with m
.If(d_out
.error
):
198 with m
.If(d_out
.cache_paradox
):
199 sync
+= self
.derror
.eq(1)
200 sync
+= self
.dsisr
[63 - 38].eq(~self
.load
)
201 # XXX there is no architected bit for this
202 # (probably should be a machine check in fact)
203 sync
+= self
.dsisr
[63 - 35].eq(d_out
.cache_paradox
)
206 # Look up the translation for TLB miss
207 # and also for permission error and RC error
208 # in case the PTE has been updated.
209 sync
+= self
.mmureq
.eq(1)
210 sync
+= self
.state
.eq(State
.MMU_LOOKUP
)
214 # happened, alignment, instr_fault, invalid.
215 # note that all of these flow through - eventually to the TRAP
216 # pipeline, via PowerDecoder2.
217 comb
+= exc
.happened
.eq(d_out
.error | l_out
.err | self
.align_intr
)
218 comb
+= exc
.invalid
.eq(l_out
.invalid
)
219 comb
+= exc
.alignment
.eq(self
.align_intr
)
221 # badtree, perm_error, rc_error, segment_fault
222 comb
+= exc
.badtree
.eq(l_out
.badtree
)
223 comb
+= exc
.perm_error
.eq(l_out
.perm_error
)
224 comb
+= exc
.rc_error
.eq(l_out
.rc_error
)
225 comb
+= exc
.segment_fault
.eq(l_out
.segerr
)
227 # TODO some exceptions set SPRs
229 # TODO, connect dcache wb_in/wb_out to "standard" nmigen Wishbone bus
230 comb
+= dbus
.adr
.eq(dcache
.wb_out
.adr
)
231 comb
+= dbus
.dat_w
.eq(dcache
.wb_out
.dat
)
232 comb
+= dbus
.sel
.eq(dcache
.wb_out
.sel
)
233 comb
+= dbus
.cyc
.eq(dcache
.wb_out
.cyc
)
234 comb
+= dbus
.stb
.eq(dcache
.wb_out
.stb
)
235 comb
+= dbus
.we
.eq(dcache
.wb_out
.we
)
237 comb
+= dcache
.wb_in
.dat
.eq(dbus
.dat_r
)
238 comb
+= dcache
.wb_in
.ack
.eq(dbus
.ack
)
239 if hasattr(dbus
, "stall"):
240 comb
+= dcache
.wb_in
.stall
.eq(dbus
.stall
)
242 # create a blip (single pulse) on valid read/write request
243 m
.d
.comb
+= self
.d_validblip
.eq(rising_edge(m
, self
.d_valid
))
245 # write out d data only when flag set
246 with m
.If(self
.d_w_valid
):
247 m
.d
.sync
+= d_in
.data
.eq(self
.store_data
)
249 m
.d
.sync
+= d_in
.data
.eq(0)
251 m
.d
.comb
+= d_in
.load
.eq(self
.load
)
252 m
.d
.comb
+= d_in
.byte_sel
.eq(self
.byte_sel
)
253 m
.d
.comb
+= d_in
.addr
.eq(self
.addr
)
254 m
.d
.comb
+= d_in
.nc
.eq(self
.nc
)
255 m
.d
.comb
+= self
.done
.eq(d_out
.valid
)
256 m
.d
.comb
+= self
.load_data
.eq(d_out
.data
)
261 yield from super().ports()
265 class TestSRAMLoadStore1(LoadStore1
):
266 def __init__(self
, pspec
):
267 super().__init
__(pspec
)
269 # small 32-entry Memory
270 if (hasattr(pspec
, "dmem_test_depth") and
271 isinstance(pspec
.dmem_test_depth
, int)):
272 depth
= pspec
.dmem_test_depth
275 print("TestSRAMBareLoadStoreUnit depth", depth
)
277 self
.mem
= Memory(width
=pspec
.reg_wid
, depth
=depth
)
279 def elaborate(self
, platform
):
280 m
= super().elaborate(platform
)
282 m
.submodules
.sram
= sram
= SRAM(memory
=self
.mem
, granularity
=8,
283 features
={'cti', 'bte', 'err'})
286 # directly connect the wishbone bus of LoadStoreUnitInterface to SRAM
287 # note: SRAM is a target (slave), dbus is initiator (master)
288 fanouts
= ['dat_w', 'sel', 'cyc', 'stb', 'we', 'cti', 'bte']
289 fanins
= ['dat_r', 'ack', 'err']
290 for fanout
in fanouts
:
291 print("fanout", fanout
, getattr(sram
.bus
, fanout
).shape(),
292 getattr(dbus
, fanout
).shape())
293 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
294 comb
+= getattr(sram
.bus
, fanout
).eq(getattr(dbus
, fanout
))
296 comb
+= getattr(dbus
, fanin
).eq(getattr(sram
.bus
, fanin
))
298 comb
+= sram
.bus
.adr
.eq(dbus
.adr
)