src/soc/fu/ldst/test/test_pipe_caller.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, MicrOp, CryIn)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13 from soc.config.endian import bigendian
  14
  15
  16 from soc.fu.test.common import TestCase
  17 from soc.fu.ldst.pipe_data import LDSTPipeSpec
  18 import random
  19
  20
  21 def get_cu_inputs(dec2, sim):
  22     """naming (res) must conform to LDSTFunctionUnit input regspec
  23     """
  24     res = {}
  25
  26     # RA
  27     reg1_ok = yield dec2.e.read_reg1.ok
  28     if reg1_ok:
  29         data1 = yield dec2.e.read_reg1.data
  30         res['ra'] = sim.gpr(data1).value
  31
  32     # RB (or immediate)
  33     reg2_ok = yield dec2.e.read_reg2.ok
  34     if reg2_ok:
  35         data2 = yield dec2.e.read_reg2.data
  36         res['rb'] = sim.gpr(data2).value
  37
  38     # RC
  39     reg3_ok = yield dec2.e.read_reg3.ok
  40     if reg3_ok:
  41         data3 = yield dec2.e.read_reg3.data
  42         res['rc'] = sim.gpr(data3).value
  43
  44     # XER.so
  45     oe = yield dec2.e.do.oe.data[0] & dec2.e.do.oe.ok
  46     if oe:
  47         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  48         res['xer_so'] = so
  49
  50     return res
  51
  52
  53 class LDSTTestCase(FHDLTestCase):
  54     test_data = []
  55
  56     def __init__(self, name):
  57         super().__init__(name)
  58         self.test_name = name
  59
  60     def run_tst_program(self, prog, initial_regs=None,
  61                         initial_sprs=None, initial_mem=None):
  62         tc = TestCase(prog, self.test_name, initial_regs, initial_sprs,
  63                       mem=initial_mem)
  64         self.test_data.append(tc)
  65
  66     def test_1_load(self):
  67         lst = ["lhz 3, 0(1)"]
  68         initial_regs = [0] * 32
  69         initial_regs[1] = 0x0004
  70         initial_regs[2] = 0x0008
  71         initial_mem = {0x0000: (0x5432123412345678, 8),
  72                        0x0008: (0xabcdef0187654321, 8),
  73                        0x0020: (0x1828384822324252, 8),
  74                         }
  75         self.run_tst_program(Program(lst, bigendian), initial_regs,
  76                              initial_mem=initial_mem)
  77
  78     def test_2_load_store(self):
  79         lst = [
  80                "stb 3, 1(2)",
  81                "lbz 4, 1(2)",
  82         ]
  83         initial_regs = [0] * 32
  84         initial_regs[1] = 0x0004
  85         initial_regs[2] = 0x0008
  86         initial_regs[3] = 0x00ee
  87         initial_mem = {0x0000: (0x5432123412345678, 8),
  88                        0x0008: (0xabcdef0187654321, 8),
  89                        0x0020: (0x1828384822324252, 8),
  90                         }
  91         self.run_tst_program(Program(lst, bigendian), initial_regs,
  92                              initial_mem=initial_mem)
  93
  94     def test_3_load_store(self):
  95         lst = ["sth 4, 0(2)",
  96                "lhz 4, 0(2)"]
  97         initial_regs = [0] * 32
  98         initial_regs[1] = 0x0004
  99         initial_regs[2] = 0x0002
 100         initial_regs[3] = 0x15eb
 101         initial_mem = {0x0000: (0x5432123412345678, 8),
 102                        0x0008: (0xabcdef0187654321, 8),
 103                        0x0020: (0x1828384822324252, 8),
 104                         }
 105         self.run_tst_program(Program(lst, bigendian), initial_regs,
 106                              initial_mem=initial_mem)
 107
 108     def test_4_load_store_rev_ext(self):
 109         lst = ["stwx 1, 4, 2",
 110                "lwbrx 3, 4, 2"]
 111         initial_regs = [0] * 32
 112         initial_regs[1] = 0x5678
 113         initial_regs[2] = 0x001c
 114         initial_regs[4] = 0x0008
 115         initial_mem = {0x0000: (0x5432123412345678, 8),
 116                        0x0008: (0xabcdef0187654321, 8),
 117                        0x0020: (0x1828384822324252, 8),
 118                         }
 119         self.run_tst_program(Program(lst, bigendian), initial_regs,
 120                              initial_mem=initial_mem)
 121
 122     def test_5_load_store_rev_ext(self):
 123         lst = ["stwbrx 1, 4, 2",
 124                "lwzx 3, 4, 2"]
 125         initial_regs = [0] * 32
 126         initial_regs[1] = 0x5678
 127         initial_regs[2] = 0x001c
 128         initial_regs[4] = 0x0008
 129         initial_mem = {0x0000: (0x5432123412345678, 8),
 130                        0x0008: (0xabcdef0187654321, 8),
 131                        0x0020: (0x1828384822324252, 8),
 132                         }
 133         self.run_tst_program(Program(lst, bigendian), initial_regs,
 134                              initial_mem=initial_mem)
 135
 136     def test_6_load_store_rev_ext(self):
 137         lst = ["stwbrx 1, 4, 2",
 138                "lwbrx 3, 4, 2"]
 139         initial_regs = [0] * 32
 140         initial_regs[1] = 0x5678
 141         initial_regs[2] = 0x001c
 142         initial_regs[4] = 0x0008
 143         initial_mem = {0x0000: (0x5432123412345678, 8),
 144                        0x0008: (0xabcdef0187654321, 8),
 145                        0x0020: (0x1828384822324252, 8),
 146                         }
 147         self.run_tst_program(Program(lst, bigendian), initial_regs,
 148                              initial_mem=initial_mem)
 149
 150     def test_7_load_store_d(self):
 151         lst = [
 152                "std 3, 0(2)",
 153                "ld 4, 0(2)",
 154         ]
 155         initial_regs = [0] * 32
 156         initial_regs[1] = 0x0004
 157         initial_regs[2] = 0x0008
 158         initial_regs[3] = 0x00ee
 159         initial_mem = {0x0000: (0x5432123412345678, 8),
 160                        0x0008: (0xabcdef0187654321, 8),
 161                        0x0020: (0x1828384822324252, 8),
 162                         }
 163         self.run_tst_program(Program(lst, bigendian), initial_regs,
 164                              initial_mem=initial_mem)
 165
 166     def test_8_load_store_d_update(self):
 167         lst = [
 168                "stdu 3, 0(2)",
 169                "ld 4, 0(2)",
 170         ]
 171         initial_regs = [0] * 32
 172         initial_regs[1] = 0x0004
 173         initial_regs[2] = 0x0008
 174         initial_regs[3] = 0x00ee
 175         initial_mem = {0x0000: (0x5432123412345678, 8),
 176                        0x0008: (0xabcdef0187654321, 8),
 177                        0x0020: (0x1828384822324252, 8),
 178                         }
 179         self.run_tst_program(Program(lst, bigendian), initial_regs,
 180                              initial_mem=initial_mem)
 181