src/soc/fu/logical/bpermd.py

   1 from nmigen import Elaboratable, Signal, Module, Repl, Cat, Const, Array
   2 from nmigen.cli import main
   3
   4
   5 class Bpermd(Elaboratable):
   6     """
   7     from POWERISA v3.1 p105, chaper 3
   8
   9     This class does a Bit Permute on a Doubleword
  10
  11     permd      RA,RS,RB
  12
  13     do i = 0 to 7
  14         index ← (RS)[8*i:8*i+7]
  15         If index < 64
  16             then perm[i]  ← (RB)[index]
  17             else permi[i] ← 0
  18     RA ←56[0] || perm[0:7]
  19
  20     Eight permuted bits are produced.
  21     For each permutedbit i where i
  22     ranges from 0 to 7 and for each
  23     byte i of RS, do the following.
  24
  25         If byte i of RS is less than
  26         64, permuted bit i is set to
  27         the bit of RB specified by
  28         byte i of RS; otherwise
  29         permuted bit i is set to 0.
  30
  31     The permuted bits are placed in
  32     the least-significant byte of RA,
  33     and the remaining bits are filled
  34     with 0s.
  35
  36     Special Registers Altered:
  37         None
  38
  39     Programming Note:
  40
  41     The fact that the permuted bit is
  42     0 if the corresponding index value
  43     exceeds 63 permits the permuted
  44     bits to be selected from a 128-bit
  45     quantity, using a single index
  46     register. For example, assume that
  47     the 128-bit quantity Q, from which
  48     the permuted bits are to be
  49     selected, is in registers r2
  50     (high-order 64 bits of Q) and r3
  51     (low-order 64 bits of Q), that the
  52     index values are in register r1,
  53     with each byte of r1 containing a
  54     value in the range 0:127, and that
  55     each byte of register r4 contains
  56     the value 64. The following code
  57     sequence selects eight permuted
  58     bits from Q and places them into
  59     the low-order byteof r6.
  60
  61     bpermd  r6,r1,r2 # select from high-order half of Q
  62     xor     r0,r1,r4 # adjust index values
  63     bpermd  r5,r0,r3 # select from low-order half of Q
  64     or      r6,r6,r5  # merge the two selections
  65    """
  66
  67     def __init__(self, width):
  68         self.width = width
  69         self.rs = Signal(width, reset_less=True)
  70         self.ra = Signal(width, reset_less=True)
  71         self.rb = Signal(width, reset_less=True)
  72
  73     def elaborate(self, platform):
  74         m = Module()
  75         perm = Signal(self.width, reset_less=True)
  76         rb64 = [Signal(1, reset_less=True, name=f"rb64_{i}") for i in range(64)]
  77         for i in range(64):
  78             m.d.comb += rb64[i].eq(self.rb[i])
  79         rb64 = Array(rb64)
  80         for i in range(8):
  81             index = self.rs[8*i:8*i+8]
  82             idx = Signal(8, name=f"idx_{i}", reset_less=True)
  83             m.d.comb += idx.eq(index)
  84             with m.If(idx < 64):
  85                 m.d.comb += perm[i].eq(rb64[idx])
  86         m.d.comb += self.ra[0:8].eq(perm)
  87         return m
  88
  89
  90 if __name__ == "__main__":
  91     bperm = Bpermd(width=64)
  92     main(bperm, ports=[bperm.rs, bperm.ra, bperm.rb])