src/soc/fu/logical/main_stage.py

   1 # This stage is intended to do most of the work of executing Logical
   2 # instructions. This is OR, AND, XOR, POPCNT, PRTY, CMPB, BPERMD, CNTLZ
   3 # however input and output stages also perform bit-negation on input(s)
   4 # and output, as well as carry and overflow generation.
   5 # This module however should not gate the carry or overflow, that's up
   6 # to the output stage
   7
   8 from nmigen import (Module, Signal, Cat, Repl, Mux, Const, Array)
   9 from nmutil.pipemodbase import PipeModBase
  10 from nmutil.clz import CLZ
  11 from soc.fu.logical.pipe_data import LogicalInputData
  12 from soc.fu.alu.pipe_data import ALUOutputData
  13 from ieee754.part.partsig import PartitionedSignal
  14 from soc.decoder.power_enums import InternalOp
  15
  16 from soc.decoder.power_fields import DecodeFields
  17 from soc.decoder.power_fieldsn import SignalBitRange
  18
  19
  20 def array_of(count, bitwidth):
  21     res = []
  22     for i in range(count):
  23         res.append(Signal(bitwidth, reset_less=True,
  24                           name=f"pop_{bitwidth}_{i}"))
  25     return res
  26
  27
  28 class LogicalMainStage(PipeModBase):
  29     def __init__(self, pspec):
  30         super().__init__(pspec, "main")
  31         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  32         self.fields.create_specs()
  33
  34     def ispec(self):
  35         return LogicalInputData(self.pspec)
  36
  37     def ospec(self):
  38         return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
  39
  40     def elaborate(self, platform):
  41         m = Module()
  42         comb = m.d.comb
  43         op, a, b, o = self.i.ctx.op, self.i.a, self.i.b, self.o.o
  44
  45         ##########################
  46         # main switch for logic ops AND, OR and XOR, cmpb, parity, and popcount
  47
  48         with m.Switch(op.insn_type):
  49
  50             ###### AND, OR, XOR #######
  51             with m.Case(InternalOp.OP_AND):
  52                 comb += o.eq(a & b)
  53             with m.Case(InternalOp.OP_OR):
  54                 comb += o.eq(a | b)
  55             with m.Case(InternalOp.OP_XOR):
  56                 comb += o.eq(a ^ b)
  57
  58             ###### cmpb #######
  59             with m.Case(InternalOp.OP_CMPB):
  60                 l = []
  61                 for i in range(8):
  62                     slc = slice(i*8, (i+1)*8)
  63                     l.append(Repl(a[slc] == b[slc], 8))
  64                 comb += o.eq(Cat(*l))
  65
  66             ###### popcount #######
  67             with m.Case(InternalOp.OP_POPCNT):
  68                 # starting from a, perform successive addition-reductions
  69                 # creating arrays big enough to store the sum, each time
  70                 pc = [a]
  71                 # QTY32 2-bit (to take 2x 1-bit sums) etc.
  72                 work = [(32, 2), (16, 3), (8, 4), (4, 5), (2, 6), (1, 7)]
  73                 for l, b in work:
  74                     pc.append(array_of(l, b))
  75                 pc8 = pc[3]     # array of 8 8-bit counts (popcntb)
  76                 pc32 = pc[5]    # array of 2 32-bit counts (popcntw)
  77                 popcnt = pc[-1] # array of 1 64-bit count (popcntd)
  78                 # cascade-tree of adds
  79                 for idx, (l, b) in enumerate(work):
  80                     for i in range(l):
  81                         stt, end = i*2, i*2+1
  82                         src, dst = pc[idx], pc[idx+1]
  83                         comb += dst[i].eq(Cat(src[stt], Const(0, 1)) +
  84                                           Cat(src[end], Const(0, 1)))
  85                 # decode operation length
  86                 with m.If(op.data_len == 1):
  87                     # popcntb - pack 8x 4-bit answers into output
  88                     for i in range(8):
  89                         comb += o[i*8:(i+1)*8].eq(pc8[i])
  90                 with m.Elif(op.data_len == 4):
  91                     # popcntw - pack 2x 5-bit answers into output
  92                     for i in range(2):
  93                         comb += o[i*32:(i+1)*32].eq(pc32[i])
  94                 with m.Else():
  95                     # popcntd - put 1x 6-bit answer into output
  96                     comb += o.eq(popcnt[0])
  97
  98             ###### parity #######
  99             with m.Case(InternalOp.OP_PRTY):
 100                 # strange instruction which XORs together the LSBs of each byte
 101                 par0 = Signal(reset_less=True)
 102                 par1 = Signal(reset_less=True)
 103                 comb += par0.eq(Cat(a[0] , a[8] , a[16], a[24]).xor())
 104                 comb += par1.eq(Cat(a[32], a[40], a[48], a[56]).xor())
 105                 with m.If(op.data_len[3] == 1):
 106                     comb += o.eq(par0 ^ par1)
 107                 with m.Else():
 108                     comb += o[0].eq(par0)
 109                     comb += o[32].eq(par1)
 110
 111             ###### cntlz #######
 112             with m.Case(InternalOp.OP_CNTZ):
 113                 XO = self.fields.FormX.XO[0:-1]
 114                 count_right = Signal(reset_less=True)
 115                 comb += count_right.eq(XO[-1])
 116
 117                 cntz_i = Signal(64, reset_less=True)
 118                 a32 = Signal(32, reset_less=True)
 119                 comb += a32.eq(a[0:32])
 120
 121                 with m.If(op.is_32bit):
 122                     comb += cntz_i.eq(Mux(count_right, a32[::-1], a32))
 123                 with m.Else():
 124                     comb += cntz_i.eq(Mux(count_right, a[::-1], a))
 125
 126                 m.submodules.clz = clz = CLZ(64)
 127                 comb += clz.sig_in.eq(cntz_i)
 128                 comb += o.eq(Mux(op.is_32bit, clz.lz-32, clz.lz))
 129
 130             ###### bpermd #######
 131             # TODO with m.Case(InternalOp.OP_BPERM): - not in microwatt
 132
 133         ###### sticky overflow and context, both pass-through #####
 134
 135         comb += self.o.xer_so.data.eq(self.i.xer_so)
 136         comb += self.o.ctx.eq(self.i.ctx)
 137
 138         return m