okaaay add a "rdflags" function which obtains the yes/no flags for each register...
[soc.git] / src / soc / fu / logical / pipeline.py
1 from nmutil.singlepipe import ControlBase
2 from nmutil.pipemodbase import PipeModBaseChain
3 from soc.fu.logical.input_stage import LogicalInputStage
4 from soc.fu.logical.main_stage import LogicalMainStage
5 from soc.fu.logical.output_stage import LogicalOutputStage
6
7 class LogicalStages(PipeModBaseChain):
8 def get_chain(self):
9 inp = LogicalInputStage(self.pspec)
10 main = LogicalMainStage(self.pspec)
11 out = LogicalOutputStage(self.pspec)
12 return [inp, main, out]
13
14
15 class LogicalBasePipe(ControlBase):
16 def __init__(self, pspec):
17 ControlBase.__init__(self)
18 self.pspec = pspec
19 self.pipe1 = LogicalStages(pspec)
20 self._eqs = self.connect([self.pipe1])
21
22 def elaborate(self, platform):
23 m = ControlBase.elaborate(self, platform)
24 m.submodules.pipe = self.pipe1
25 m.d.comb += self._eqs
26 return m