src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from nmigen import Const
   3 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   4 from nmutil.singlepipe import ControlBase
   5 from nmutil.util import rising_edge
   6
   7 from soc.experiment.mmu import MMU
   8 from soc.experiment.dcache import DCache
   9
  10 from soc.decoder.power_fields import DecodeFields
  11 from soc.decoder.power_fieldsn import SignalBitRange
  12 from soc.decoder.power_decoder2 import decode_spr_num
  13 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  14
  15 from soc.experiment.pimem import PortInterface
  16 from soc.experiment.pimem import PortInterfaceBase
  17
  18 from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
  19 from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
  20
  21 # for testing purposes
  22 from soc.experiment.testmem import TestMemory
  23
  24 # glue logic for microwatt mmu and dcache
  25 class LoadStore1(PortInterfaceBase):
  26     def __init__(self, regwid=64, addrwid=4):
  27         super().__init__(regwid, addrwid)
  28         self.d_in  = LoadStore1ToDCacheType()
  29         self.d_out = DCacheToLoadStore1Type()
  30         self.l_in  = LoadStore1ToMMUType()
  31         self.l_out = MMUToLoadStore1Type()
  32         # for debugging with gtkwave only
  33         self.debug1 = Signal()
  34         self.debug2 = Signal()
  35
  36     def set_wr_addr(self, m, addr, mask):
  37         #m.d.comb += self.d_in.valid.eq(1)
  38         #m.d.comb += self.l_in.valid.eq(1)
  39         #m.d.comb += self.d_in.load.eq(0)
  40         #m.d.comb += self.l_in.load.eq(0)
  41         # set phys addr on both units
  42         m.d.comb += self.d_in.addr.eq(addr)
  43         m.d.comb += self.l_in.addr.eq(addr)
  44         # TODO set mask
  45         return None
  46
  47     def set_rd_addr(self, m, addr, mask):
  48         m.d.comb += self.d_in.valid.eq(1)
  49         m.d.comb += self.l_in.valid.eq(1)
  50         m.d.comb += self.d_in.load.eq(1)
  51         m.d.comb += self.l_in.load.eq(1)
  52         m.d.comb += self.d_in.addr.eq(addr)
  53         m.d.comb += self.l_in.addr.eq(addr)
  54         m.d.comb += self.debug1.eq(1)
  55         # m.d.comb += self.debug2.eq(1)
  56         # connect testmem first
  57         return None #FIXME return value
  58
  59     def set_wr_data(self, m, data, wen):
  60         m.d.comb += self.d_in.data.eq(data)
  61         # TODO set wen
  62         st_ok = Const(1, 1)
  63         return st_ok
  64
  65     def get_rd_data(self, m):
  66         ld_ok = Const(1, 1)
  67         data = self.d_out.data
  68         return data, ld_ok
  69
  70     """
  71     if d_in.error = '1' then
  72                 if d_in.cache_paradox = '1' then
  73                     -- signal an interrupt straight away
  74                     exception := '1';
  75                     dsisr(63 - 38) := not r2.req.load;
  76                     -- XXX there is no architected bit for this
  77                     -- (probably should be a machine check in fact)
  78                     dsisr(63 - 35) := d_in.cache_paradox;
  79                 else
  80                     -- Look up the translation for TLB miss
  81                     -- and also for permission error and RC error
  82                     -- in case the PTE has been updated.
  83                     mmureq := '1';
  84                     v.state := MMU_LOOKUP;
  85                     v.stage1_en := '0';
  86                 end if;
  87             end if;
  88     """
  89
  90     def elaborate(self, platform):
  91         m = super().elaborate(platform)
  92
  93         d_out = self.d_out
  94         l_out = self.l_out
  95
  96         exc = self.pi.exception_o
  97
  98         #happened, alignment, instr_fault, invalid,
  99         m.d.comb += exc.happened.eq(d_out.error | l_out.err)
 100         m.d.comb += exc.invalid.eq(l_out.invalid)
 101
 102         #badtree, perm_error, rc_error, segment_fault
 103         m.d.comb += exc.badtree.eq(l_out.badtree)
 104         m.d.comb += exc.perm_error.eq(l_out.perm_error)
 105         m.d.comb += exc.rc_error.eq(l_out.rc_error)
 106         m.d.comb += exc.segment_fault.eq(l_out.segerr)
 107
 108         # TODO connect those signals somewhere
 109         #print(d_out.valid)         -> no error
 110         #print(d_out.store_done)    -> no error
 111         #print(d_out.cache_paradox) -> ?
 112         #print(l_out.done)          -> no error
 113
 114         # TODO some exceptions set SPRs
 115
 116         return m
 117
 118     def ports(self):
 119         yield from super().ports()
 120         # TODO: memory ports
 121
 122 class FSMMMUStage(ControlBase):
 123     def __init__(self, pspec):
 124         super().__init__()
 125         self.pspec = pspec
 126
 127         # set up p/n data
 128         self.p.data_i = MMUInputData(pspec)
 129         self.n.data_o = MMUOutputData(pspec)
 130
 131         # incoming PortInterface
 132         self.ldst = LoadStore1()       # TODO make this depend on pspec
 133         self.pi = self.ldst.pi
 134
 135         # this Function Unit is extremely unusual in that it actually stores a
 136         # "thing" rather than "processes inputs and produces outputs".  hence
 137         # why it has to be a FSM.  linking up LD/ST however is going to have
 138         # to be done back in Issuer (or Core)
 139
 140         self.mmu = MMU()
 141         self.dcache = DCache()
 142         regwid=64
 143         aw = 5
 144         # for verification of DCache
 145         # TODO: create connection to real memory, backend memory interface
 146         self.testmem = TestMemory(regwid, aw, granularity=regwid//8, init=False)
 147
 148         # make life a bit easier in Core
 149         self.pspec.mmu = self.mmu
 150         self.pspec.dcache = self.dcache
 151
 152         # debugging output for gtkw
 153         self.debug0 = Signal(4)
 154         self.debug_wb_cyc = Signal()
 155         self.debug_wb_stb = Signal()
 156         self.debug_wb_we = Signal()
 157         self.debug1 = Signal()
 158         #self.debug2 = Signal(64)
 159         #self.debug3 = Signal(64)
 160         self.illegal = Signal()
 161
 162         # for SPR field number access
 163         i = self.p.data_i
 164         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
 165         self.fields.create_specs()
 166
 167     def elaborate(self, platform):
 168         m = super().elaborate(platform)
 169         comb = m.d.comb
 170
 171         # link mmu and dcache together
 172         m.submodules.dcache = dcache = self.dcache
 173         m.submodules.mmu = mmu = self.mmu
 174         m.submodules.ldst = ldst = self.ldst
 175         m.submodules.testmem = testmem = self.testmem
 176         m.d.comb += dcache.m_in.eq(mmu.d_out)
 177         m.d.comb += mmu.d_in.eq(dcache.m_out)
 178         l_in, l_out = mmu.l_in, mmu.l_out
 179         d_in, d_out = dcache.d_in, dcache.d_out
 180         wb_out, wb_in = dcache.wb_out, dcache.wb_in
 181
 182         # link ldst and dcache together
 183         comb += l_in.eq(self.ldst.l_in)
 184         comb += self.ldst.l_out.eq(l_out)
 185         comb += d_in.eq(self.ldst.d_in)
 186         comb += self.ldst.d_out.eq(self.dcache.d_out)
 187
 188         #connect read port
 189         rdport = self.testmem.rdport
 190         comb += rdport.addr.eq(wb_out.adr)
 191         comb += wb_in.dat.eq(rdport.data)
 192
 193         #connect write port
 194         wrport = self.testmem.wrport
 195         comb += wrport.addr.eq(wb_out.adr)
 196         comb += wrport.data.eq(wb_out.dat) # write st to mem
 197         comb += wrport.en.eq(wb_out.cyc & wb_out.we) # enable writes
 198
 199         # connect DCache wishbone master to debugger
 200         comb += self.debug_wb_cyc.eq(wb_out.cyc)
 201         comb += self.debug_wb_stb.eq(wb_out.stb)
 202         comb += self.debug_wb_we.eq(wb_out.we)
 203
 204         comb += wb_in.stall.eq(0)
 205         # testmem only takes on cycle
 206         with m.If( wb_out.cyc ):
 207             m.d.sync += wb_in.ack.eq( wb_out.stb )
 208
 209         data_i, data_o = self.p.data_i, self.n.data_o
 210         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
 211         op = data_i.ctx.op
 212
 213         # TODO: link these SPRs somewhere
 214         dsisr = Signal(64)
 215         dar = Signal(64)
 216
 217         # busy/done signals
 218         busy = Signal()
 219         done = Signal()
 220         m.d.comb += self.n.valid_o.eq(busy & done)
 221         m.d.comb += self.p.ready_o.eq(~busy)
 222
 223         # take copy of X-Form SPR field
 224         x_fields = self.fields.FormXFX
 225         spr = Signal(len(x_fields.SPR))
 226         comb += spr.eq(decode_spr_num(x_fields.SPR))
 227
 228         # ok so we have to "pulse" the MMU (or dcache) rather than
 229         # hold the valid hi permanently.  guess what this does...
 230         valid = Signal()
 231         blip = Signal()
 232         m.d.comb += blip.eq(rising_edge(m, valid))
 233
 234         with m.If(~busy):
 235             with m.If(self.p.valid_i):
 236                 m.d.sync += busy.eq(1)
 237         with m.Else():
 238
 239             # based on the Micro-Op, we work out which of MMU or DCache
 240             # should "action" the operation.  one of MMU or DCache gets
 241             # enabled ("valid") and we twiddle our thumbs until it
 242             # responds ("done").
 243
 244             # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 245
 246             with m.Switch(op.insn_type):
 247                 with m.Case(MicrOp.OP_MTSPR):
 248                     # subset SPR: first check a few bits
 249                     with m.If(~spr[9] & ~spr[5]):
 250                         comb += self.debug0.eq(3)
 251                         with m.If(spr[0]):
 252                             comb += dsisr.eq(a_i[:32])
 253                         with m.Else():
 254                             comb += dar.eq(a_i)
 255                         comb += done.eq(1)
 256                     # pass it over to the MMU instead
 257                     with m.Else():
 258                         comb += self.debug0.eq(4)
 259                         # blip the MMU and wait for it to complete
 260                         comb += valid.eq(1)   # start "pulse"
 261                         comb += l_in.valid.eq(blip)   # start
 262                         comb += l_in.mtspr.eq(1)      # mtspr mode
 263                         comb += l_in.sprn.eq(spr)  # which SPR
 264                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 265                         comb += done.eq(1) # FIXME l_out.done
 266
 267                 with m.Case(MicrOp.OP_MFSPR):
 268                     # subset SPR: first check a few bits
 269                     with m.If(~spr[9] & ~spr[5]):
 270                         comb += self.debug0.eq(5)
 271                         with m.If(spr[0]):
 272                             comb += o.data.eq(dsisr)
 273                         with m.Else():
 274                             comb += o.data.eq(dar)
 275                         #FIXME comb += o.ok.eq(1)
 276                         comb += done.eq(1)
 277                     # pass it over to the MMU instead
 278                     with m.Else():
 279                         comb += self.debug0.eq(6)
 280                         # blip the MMU and wait for it to complete
 281                         comb += valid.eq(1)   # start "pulse"
 282                         comb += l_in.valid.eq(blip)   # start
 283                         comb += l_in.mtspr.eq(0)   # mfspr!=mtspr
 284                         comb += l_in.sprn.eq(spr)  # which SPR
 285                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 286                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 287                         comb += o.ok.eq(l_out.done) # only when l_out valid
 288                         comb += done.eq(1) # FIXME l_out.done
 289
 290                 with m.Case(MicrOp.OP_DCBZ):
 291                     # activate dcbz mode (spec: v3.0B p850)
 292                     comb += valid.eq(1)   # start "pulse"
 293                     comb += d_in.valid.eq(blip)     # start
 294                     comb += d_in.dcbz.eq(1)         # dcbz mode
 295                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 296                     comb += done.eq(d_out.store_done)     # TODO
 297                     comb += self.debug0.eq(1)
 298
 299                 with m.Case(MicrOp.OP_TLBIE):
 300                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 301                     # note that the spr is *not* an actual spr number, it's
 302                     # just that those bits happen to match with field bits
 303                     # RIC, PRS, R
 304                     comb += valid.eq(1)   # start "pulse"
 305                     comb += l_in.valid.eq(blip)   # start
 306                     comb += l_in.tlbie.eq(1)   # mtspr mode
 307                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 308                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 309                     comb += done.eq(l_out.done) # zzzz
 310                     comb += self.debug0.eq(2)
 311                 with m.Case(MicrOp.OP_ILLEGAL):
 312                     comb += self.illegal.eq(1)
 313
 314             with m.If(self.n.ready_i & self.n.valid_o):
 315                 m.d.sync += busy.eq(0)
 316
 317         return m
 318
 319     def __iter__(self):
 320         yield from self.p
 321         yield from self.n
 322
 323     def ports(self):
 324         return list(self)