src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   3 from nmutil.singlepipe import ControlBase
   4 from nmutil.util import rising_edge
   5
   6 from soc.experiment.mmu import MMU
   7 from soc.experiment.dcache import DCache
   8
   9 from soc.decoder.power_fields import DecodeFields
  10 from soc.decoder.power_fieldsn import SignalBitRange
  11 from soc.decoder.power_decoder2 import decode_spr_num
  12 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  13
  14
  15 class FSMMMUStage(ControlBase):
  16     def __init__(self, pspec):
  17         super().__init__()
  18         self.pspec = pspec
  19
  20         # set up p/n data
  21         self.p.data_i = MMUInputData(pspec)
  22         self.n.data_o = MMUOutputData(pspec)
  23
  24         # this Function Unit is extremely unusual in that it actually stores a
  25         # "thing" rather than "processes inputs and produces outputs".  hence
  26         # why it has to be a FSM.  linking up LD/ST however is going to have
  27         # to be done back in Issuer (or Core)
  28
  29         self.mmu = MMU()
  30         self.dcache = DCache()
  31
  32         # make life a bit easier in Core
  33         self.pspec.mmu = self.mmu
  34         self.pspec.dcache = self.dcache
  35
  36         # for SPR field number access
  37         i = self.p.data_i
  38         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
  39         self.fields.create_specs()
  40
  41     def elaborate(self, platform):
  42         m = super().elaborate(platform)
  43         comb = m.d.comb
  44
  45         # link mmu and dcache together
  46         m.submodules.dcache = dcache = self.dcache
  47         m.submodules.mmu = mmu = self.mmu
  48         m.d.comb += dcache.m_in.eq(mmu.d_out)
  49         m.d.comb += mmu.d_in.eq(dcache.m_out)
  50         l_in, l_out = mmu.l_in, mmu.l_out
  51         d_in, d_out = dcache.d_in, dcache.d_out
  52
  53         data_i, data_o = self.p.data_i, self.n.data_o
  54         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
  55         op = data_i.ctx.op
  56
  57         # TODO: link these SPRs somewhere
  58         dsisr = Signal(64)
  59         dar = Signal(64)
  60
  61         # busy/done signals
  62         busy = Signal()
  63         done = Signal()
  64         m.d.comb += self.n.valid_o.eq(busy & done)
  65         m.d.comb += self.p.ready_o.eq(~busy)
  66
  67         # take copy of X-Form SPR field
  68         x_fields = self.fields.FormXFX
  69         spr = Signal(len(x_fields.SPR))
  70         comb += spr.eq(decode_spr_num(x_fields.SPR))
  71
  72         # ok so we have to "pulse" the MMU (or dcache) rather than
  73         # hold the valid hi permanently.  guess what this does...
  74         valid = Signal()
  75         blip = Signal()
  76         m.d.comb += blip.eq(rising_edge(m, valid))
  77
  78         with m.If(~busy):
  79             with m.If(self.p.valid_i):
  80                 m.d.sync += busy.eq(1)
  81         with m.Else():
  82
  83             # based on the Micro-Op, we work out which of MMU or DCache
  84             # should "action" the operation.  one of MMU or DCache gets
  85             # enabled ("valid") and we twiddle our thumbs until it
  86             # responds ("done").
  87             with m.Switch(op):
  88
  89                 with m.Case(MicrOp.OP_MTSPR):
  90                     # subset SPR: first check a few bits
  91                     with m.If(~spr[9] & ~spr[5]):
  92                         with m.If(spr[0]):
  93                             comb += dsisr.eq(a_i[:32])
  94                         with m.Else():
  95                             comb += dar.eq(a_i)
  96                         comb += done.eq(1)
  97                     # pass it over to the MMU instead
  98                     with m.Else():
  99                         # blip the MMU and wait for it to complete
 100                         comb += valid.eq(1)   # start "pulse"
 101                         comb += l_in.valid.eq(blip)   # start
 102                         comb += l_in.mtspr.eq(1)      # mtspr mode
 103                         comb += l_in.sprn.eq(spr)  # which SPR
 104                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 105                         comb += done.eq(l_out.done) # zzzz
 106
 107                 with m.Case(MicrOp.OP_MFSPR):
 108                     # subset SPR: first check a few bits
 109                     with m.If(~spr[9] & ~spr[5]):
 110                         with m.If(spr[0]):
 111                             comb += o.data.eq(dsisr)
 112                         with m.Else():
 113                             comb += o.data.eq(dar)
 114                         comb += o.ok.eq(1)
 115                         comb += done.eq(1)
 116                     # pass it over to the MMU instead
 117                     with m.Else():
 118                         # blip the MMU and wait for it to complete
 119                         comb += valid.eq(1)   # start "pulse"
 120                         comb += l_in.valid.eq(blip)   # start
 121                         comb += l_in.mtspr.eq(1)   # mtspr mode
 122                         comb += l_in.sprn.eq(spr)  # which SPR
 123                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 124                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 125                         comb += o.ok.eq(l_out.done) # only when l_out valid
 126                         comb += done.eq(l_out.done) # zzzz
 127
 128                 with m.Case(MicrOp.OP_DCBZ):
 129                     # activate dcbz mode (spec: v3.0B p850)
 130                     comb += valid.eq(1)   # start "pulse"
 131                     comb += d_in.valid.eq(blip)     # start
 132                     comb += d_in.dcbz.eq(1)         # dcbz mode
 133                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 134                     comb += done.eq(l_out.done)     # zzzz
 135
 136                 with m.Case(MicrOp.OP_TLBIE):
 137                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 138                     # note that the spr is *not* an actual spr number, it's
 139                     # just that those bits happen to match with field bits
 140                     # RIC, PRS, R
 141                     comb += valid.eq(1)   # start "pulse"
 142                     comb += l_in.valid.eq(blip)   # start
 143                     comb += l_in.tlbie.eq(1)   # mtspr mode
 144                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 145                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 146                     comb += done.eq(l_out.done) # zzzz
 147
 148             with m.If(self.n.ready_i & self.n.valid_o):
 149                 m.d.sync += busy.eq(0)
 150
 151         return m
 152
 153     def __iter__(self):
 154         yield from self.p
 155         yield from self.n
 156
 157     def ports(self):
 158         return list(self)