src/soc/fu/mmu/fsm.py

   1 from nmigen import Elaboratable, Module, Signal, Shape, unsigned, Cat, Mux
   2 from nmigen import Const
   3 from soc.fu.mmu.pipe_data import MMUInputData, MMUOutputData, MMUPipeSpec
   4 from nmutil.singlepipe import ControlBase
   5 from nmutil.util import rising_edge
   6
   7 from soc.experiment.mmu import MMU
   8 from soc.experiment.dcache import DCache
   9
  10 from soc.decoder.power_fields import DecodeFields
  11 from soc.decoder.power_fieldsn import SignalBitRange
  12 from soc.decoder.power_decoder2 import decode_spr_num
  13 from soc.decoder.power_enums import MicrOp, SPR, XER_bits
  14
  15 from soc.experiment.pimem import PortInterface
  16 from soc.experiment.pimem import PortInterfaceBase
  17
  18 from soc.experiment.mem_types import LoadStore1ToDCacheType, LoadStore1ToMMUType
  19 from soc.experiment.mem_types import DCacheToLoadStore1Type, MMUToLoadStore1Type
  20
  21 # for testing purposes
  22 from soc.experiment.testmem import TestMemory
  23
  24 # glue logic for microwatt mmu and dcache
  25 class LoadStore1(PortInterfaceBase):
  26     def __init__(self, regwid=64, addrwid=4):
  27         super().__init__(regwid, addrwid)
  28         self.d_in  = LoadStore1ToDCacheType()
  29         self.d_out = DCacheToLoadStore1Type()
  30         self.l_in  = LoadStore1ToMMUType()
  31         self.l_out = MMUToLoadStore1Type()
  32         # for debugging with gtkwave only
  33         self.debug1 = Signal()
  34         self.debug2 = Signal()
  35         # TODO microwatt
  36         self.mmureq = Signal()
  37         self.derror = Signal()
  38
  39     def set_wr_addr(self, m, addr, mask):
  40         #m.d.comb += self.d_in.valid.eq(1)
  41         #m.d.comb += self.l_in.valid.eq(1)
  42         #m.d.comb += self.d_in.load.eq(0)
  43         #m.d.comb += self.l_in.load.eq(0)
  44         # set phys addr on both units
  45         m.d.comb += self.d_in.addr.eq(addr)
  46         m.d.comb += self.l_in.addr.eq(addr)
  47         # TODO set mask
  48         return None
  49
  50     def set_rd_addr(self, m, addr, mask):
  51         m.d.comb += self.d_in.valid.eq(1)
  52         m.d.comb += self.l_in.valid.eq(1)
  53         m.d.comb += self.d_in.load.eq(1)
  54         m.d.comb += self.l_in.load.eq(1)
  55         m.d.comb += self.d_in.addr.eq(addr)
  56         m.d.comb += self.l_in.addr.eq(addr)
  57         m.d.comb += self.debug1.eq(1)
  58         # m.d.comb += self.debug2.eq(1)
  59         # connect testmem first
  60         return None #FIXME return value
  61
  62     def set_wr_data(self, m, data, wen):
  63         m.d.comb += self.d_in.data.eq(data)
  64         # TODO set wen
  65         st_ok = Const(1, 1)
  66         return st_ok
  67
  68     def get_rd_data(self, m):
  69         ld_ok = Const(1, 1)
  70         data = self.d_out.data
  71         return data, ld_ok
  72
  73     """
  74     if d_in.error = '1' then
  75                 if d_in.cache_paradox = '1' then
  76                     -- signal an interrupt straight away
  77                     exception := '1';
  78                     dsisr(63 - 38) := not r2.req.load;
  79                     -- XXX there is no architected bit for this
  80                     -- (probably should be a machine check in fact)
  81                     dsisr(63 - 35) := d_in.cache_paradox;
  82                 else
  83                     -- Look up the translation for TLB miss
  84                     -- and also for permission error and RC error
  85                     -- in case the PTE has been updated.
  86                     mmureq := '1';
  87                     v.state := MMU_LOOKUP;
  88                     v.stage1_en := '0';
  89                 end if;
  90             end if;
  91     """
  92
  93     def elaborate(self, platform):
  94         m = super().elaborate(platform)
  95
  96         d_out = self.d_out
  97         l_out = self.l_out
  98
  99         with m.If(d_out.error):
 100             with m.If(d_out.cache_paradox):
 101                 m.d.comb += self.derror.eq(1)
 102                 #  dsisr(63 - 38) := not r2.req.load;
 103                 #    -- XXX there is no architected bit for this
 104                 #    -- (probably should be a machine check in fact)
 105                 #    dsisr(63 - 35) := d_in.cache_paradox;
 106             with m.Else():
 107                 # Look up the translation for TLB miss
 108                 # and also for permission error and RC error
 109                 # in case the PTE has been updated.
 110                 m.d.comb += self.mmureq.eq(1)
 111                 # v.state := MMU_LOOKUP;
 112                 # v.stage1_en := '0';
 113
 114         exc = self.pi.exception_o
 115
 116         #happened, alignment, instr_fault, invalid,
 117         m.d.comb += exc.happened.eq(d_out.error | l_out.err)
 118         m.d.comb += exc.invalid.eq(l_out.invalid)
 119
 120         #badtree, perm_error, rc_error, segment_fault
 121         m.d.comb += exc.badtree.eq(l_out.badtree)
 122         m.d.comb += exc.perm_error.eq(l_out.perm_error)
 123         m.d.comb += exc.rc_error.eq(l_out.rc_error)
 124         m.d.comb += exc.segment_fault.eq(l_out.segerr)
 125
 126         # TODO connect those signals somewhere
 127         #print(d_out.valid)         -> no error
 128         #print(d_out.store_done)    -> no error
 129         #print(d_out.cache_paradox) -> ?
 130         #print(l_out.done)          -> no error
 131
 132         # TODO some exceptions set SPRs
 133
 134         return m
 135
 136     def ports(self):
 137         yield from super().ports()
 138         # TODO: memory ports
 139
 140 class FSMMMUStage(ControlBase):
 141     def __init__(self, pspec):
 142         super().__init__()
 143         self.pspec = pspec
 144
 145         # set up p/n data
 146         self.p.data_i = MMUInputData(pspec)
 147         self.n.data_o = MMUOutputData(pspec)
 148
 149         # incoming PortInterface
 150         self.ldst = LoadStore1()       # TODO make this depend on pspec
 151         self.pi = self.ldst.pi
 152
 153         # this Function Unit is extremely unusual in that it actually stores a
 154         # "thing" rather than "processes inputs and produces outputs".  hence
 155         # why it has to be a FSM.  linking up LD/ST however is going to have
 156         # to be done back in Issuer (or Core)
 157
 158         self.mmu = MMU()
 159         self.dcache = DCache()
 160         regwid=64
 161         aw = 5
 162         # for verification of DCache
 163         # TODO: create connection to real memory, backend memory interface
 164         self.testmem = TestMemory(regwid, aw, granularity=regwid//8, init=False)
 165
 166         # make life a bit easier in Core
 167         self.pspec.mmu = self.mmu
 168         self.pspec.dcache = self.dcache
 169
 170         # debugging output for gtkw
 171         self.debug0 = Signal(4)
 172         self.debug_wb_cyc = Signal()
 173         self.debug_wb_stb = Signal()
 174         self.debug_wb_we = Signal()
 175         self.debug1 = Signal()
 176         #self.debug2 = Signal(64)
 177         #self.debug3 = Signal(64)
 178         self.illegal = Signal()
 179
 180         # for SPR field number access
 181         i = self.p.data_i
 182         self.fields = DecodeFields(SignalBitRange, [i.ctx.op.insn])
 183         self.fields.create_specs()
 184
 185     def elaborate(self, platform):
 186         m = super().elaborate(platform)
 187         comb = m.d.comb
 188
 189         # link mmu and dcache together
 190         m.submodules.dcache = dcache = self.dcache
 191         m.submodules.mmu = mmu = self.mmu
 192         m.submodules.ldst = ldst = self.ldst
 193         m.submodules.testmem = testmem = self.testmem
 194         m.d.comb += dcache.m_in.eq(mmu.d_out)
 195         m.d.comb += mmu.d_in.eq(dcache.m_out)
 196         l_in, l_out = mmu.l_in, mmu.l_out
 197         d_in, d_out = dcache.d_in, dcache.d_out
 198         wb_out, wb_in = dcache.wb_out, dcache.wb_in
 199
 200         # link ldst and dcache together
 201         comb += l_in.eq(self.ldst.l_in)
 202         comb += self.ldst.l_out.eq(l_out)
 203         comb += d_in.eq(self.ldst.d_in)
 204         comb += self.ldst.d_out.eq(self.dcache.d_out)
 205
 206         #connect read port
 207         rdport = self.testmem.rdport
 208         comb += rdport.addr.eq(wb_out.adr)
 209         comb += wb_in.dat.eq(rdport.data)
 210
 211         #connect write port
 212         wrport = self.testmem.wrport
 213         comb += wrport.addr.eq(wb_out.adr)
 214         comb += wrport.data.eq(wb_out.dat) # write st to mem
 215         comb += wrport.en.eq(wb_out.cyc & wb_out.we) # enable writes
 216
 217         # connect DCache wishbone master to debugger
 218         comb += self.debug_wb_cyc.eq(wb_out.cyc)
 219         comb += self.debug_wb_stb.eq(wb_out.stb)
 220         comb += self.debug_wb_we.eq(wb_out.we)
 221
 222         comb += wb_in.stall.eq(0)
 223         # testmem only takes on cycle
 224         with m.If( wb_out.cyc ):
 225             m.d.sync += wb_in.ack.eq( wb_out.stb )
 226
 227         data_i, data_o = self.p.data_i, self.n.data_o
 228         a_i, b_i, o = data_i.ra, data_i.rb, data_o.o
 229         op = data_i.ctx.op
 230
 231         # TODO: link these SPRs somewhere
 232         dsisr = Signal(64)
 233         dar = Signal(64)
 234
 235         # busy/done signals
 236         busy = Signal()
 237         done = Signal()
 238         m.d.comb += self.n.valid_o.eq(busy & done)
 239         m.d.comb += self.p.ready_o.eq(~busy)
 240
 241         # take copy of X-Form SPR field
 242         x_fields = self.fields.FormXFX
 243         spr = Signal(len(x_fields.SPR))
 244         comb += spr.eq(decode_spr_num(x_fields.SPR))
 245
 246         # ok so we have to "pulse" the MMU (or dcache) rather than
 247         # hold the valid hi permanently.  guess what this does...
 248         valid = Signal()
 249         blip = Signal()
 250         m.d.comb += blip.eq(rising_edge(m, valid))
 251
 252         with m.If(~busy):
 253             with m.If(self.p.valid_i):
 254                 m.d.sync += busy.eq(1)
 255         with m.Else():
 256
 257             # based on the Micro-Op, we work out which of MMU or DCache
 258             # should "action" the operation.  one of MMU or DCache gets
 259             # enabled ("valid") and we twiddle our thumbs until it
 260             # responds ("done").
 261
 262             # FIXME: properly implement MicrOp.OP_MTSPR and MicrOp.OP_MFSPR
 263
 264             with m.Switch(op.insn_type):
 265                 with m.Case(MicrOp.OP_MTSPR):
 266                     # subset SPR: first check a few bits
 267                     with m.If(~spr[9] & ~spr[5]):
 268                         comb += self.debug0.eq(3)
 269                         with m.If(spr[0]):
 270                             comb += dsisr.eq(a_i[:32])
 271                         with m.Else():
 272                             comb += dar.eq(a_i)
 273                         comb += done.eq(1)
 274                     # pass it over to the MMU instead
 275                     with m.Else():
 276                         comb += self.debug0.eq(4)
 277                         # blip the MMU and wait for it to complete
 278                         comb += valid.eq(1)   # start "pulse"
 279                         comb += l_in.valid.eq(blip)   # start
 280                         comb += l_in.mtspr.eq(1)      # mtspr mode
 281                         comb += l_in.sprn.eq(spr)  # which SPR
 282                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 283                         comb += done.eq(1) # FIXME l_out.done
 284
 285                 with m.Case(MicrOp.OP_MFSPR):
 286                     # subset SPR: first check a few bits
 287                     with m.If(~spr[9] & ~spr[5]):
 288                         comb += self.debug0.eq(5)
 289                         with m.If(spr[0]):
 290                             comb += o.data.eq(dsisr)
 291                         with m.Else():
 292                             comb += o.data.eq(dar)
 293                         #FIXME comb += o.ok.eq(1)
 294                         comb += done.eq(1)
 295                     # pass it over to the MMU instead
 296                     with m.Else():
 297                         comb += self.debug0.eq(6)
 298                         # blip the MMU and wait for it to complete
 299                         comb += valid.eq(1)   # start "pulse"
 300                         comb += l_in.valid.eq(blip)   # start
 301                         comb += l_in.mtspr.eq(0)   # mfspr!=mtspr
 302                         comb += l_in.sprn.eq(spr)  # which SPR
 303                         comb += l_in.rs.eq(a_i)    # incoming operand (RS)
 304                         comb += o.data.eq(l_out.sprval) # SPR from MMU
 305                         comb += o.ok.eq(l_out.done) # only when l_out valid
 306                         comb += done.eq(1) # FIXME l_out.done
 307
 308                 with m.Case(MicrOp.OP_DCBZ):
 309                     # activate dcbz mode (spec: v3.0B p850)
 310                     comb += valid.eq(1)   # start "pulse"
 311                     comb += d_in.valid.eq(blip)     # start
 312                     comb += d_in.dcbz.eq(1)         # dcbz mode
 313                     comb += d_in.addr.eq(a_i + b_i) # addr is (RA|0) + RB
 314                     comb += done.eq(d_out.store_done)     # TODO
 315                     comb += self.debug0.eq(1)
 316
 317                 with m.Case(MicrOp.OP_TLBIE):
 318                     # pass TLBIE request to MMU (spec: v3.0B p1034)
 319                     # note that the spr is *not* an actual spr number, it's
 320                     # just that those bits happen to match with field bits
 321                     # RIC, PRS, R
 322                     comb += valid.eq(1)   # start "pulse"
 323                     comb += l_in.valid.eq(blip)   # start
 324                     comb += l_in.tlbie.eq(1)   # mtspr mode
 325                     comb += l_in.sprn.eq(spr)  # use sprn to send insn bits
 326                     comb += l_in.addr.eq(b_i)  # incoming operand (RB)
 327                     comb += done.eq(l_out.done) # zzzz
 328                     comb += self.debug0.eq(2)
 329                 with m.Case(MicrOp.OP_ILLEGAL):
 330                     comb += self.illegal.eq(1)
 331
 332             with m.If(self.n.ready_i & self.n.valid_o):
 333                 m.d.sync += busy.eq(0)
 334
 335         return m
 336
 337     def __iter__(self):
 338         yield from self.p
 339         yield from self.n
 340
 341     def ports(self):
 342         return list(self)